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Change subject: soc/amd/block/ivrs: Add NULL check for IVRS
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Patch Set 4: Code-Review+2
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Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs
......................................................................
Patch Set 13:
(1 comment)
Patchset:
PS13:
> Much thanks for helping to review the code very throughly even if this is just mainboard code - @Fel […]
Missed out Kyösti Mälkki and Jonathan.
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Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs
......................................................................
Patch Set 13:
(1 comment)
Patchset:
PS13:
Much thanks for helping to review the code very throughly even if this is just mainboard code - @Felix Singer, Felix Held, Nico Huber & Paul Menzel. This really improves the code quality and give confidence for people to keep upstreaming and working with upstreamed code!
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Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs
......................................................................
Patch Set 13: Code-Review+2
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Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs
......................................................................
Patch Set 13:
(1 comment)
File src/mainboard/bytedance/bd_egs/Kconfig:
https://review.coreboot.org/c/coreboot/+/75722/comment/aab16d51_08adf4ae :
PS10, Line 32: default "\\_SB.C%03d"
> Hi Sheng, […]
Thanks for helping to check! I will mark it as resolved now since it is removed, feel free to reopen if have any concern.
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Change subject: smm: Invalid the smm handler region instead of the whole
......................................................................
Patch Set 5: Code-Review-2
(1 comment)
Patchset:
PS4:
> The whole point of using TSEG as a stage cache is that the OS can't touch it. […]
ping. This is the reason for my -2.
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Hello Reka Norman, Ryan Lin, Sumeet R Pawnikar, Zhuohao Lee, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75681?usp=email
to look at the new patch set (#12).
Change subject: mb/google/dedede/var/dibbi: Update power limits
......................................................................
mb/google/dedede/var/dibbi: Update power limits
Add ramstage.c in Makefile.inc and update Dibbi power limits in Dibbi ramstage.c.
BUG=b:281479111
TEST=emerge-dedede coreboot and check psys and PLx value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com>
Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6
---
M src/mainboard/google/dedede/variants/dibbi/Makefile.inc
A src/mainboard/google/dedede/variants/dibbi/ramstage.c
2 files changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/75681/12
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