coreboot-gerrit June 2023

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[M] Change in coreboot[master]: vendorcode/amd/fsp/phoenix: Add dmi_info.h header
by Konrad Adamczyk (Code Review) 27 Jun '23

27 Jun '23

Konrad Adamczyk has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76107?usp=email ) Change subject: vendorcode/amd/fsp/phoenix: Add dmi_info.h header ...................................................................... vendorcode/amd/fsp/phoenix: Add dmi_info.h header BUG=b:288520486 TEST=In kernel, dump `dmidecode -t 17`. Signed-off-by: Konrad Adamczyk <konrada(a)google.com> Change-Id: I5e0109af51b78360f7038b20a2975aceb721a7d5 --- A src/vendorcode/amd/fsp/phoenix/dmi_info.h 1 file changed, 240 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/76107/1 diff --git a/src/vendorcode/amd/fsp/phoenix/dmi_info.h b/src/vendorcode/amd/fsp/phoenix/dmi_info.h new file mode 100644 index 0000000..cd76857 --- /dev/null +++ b/src/vendorcode/amd/fsp/phoenix/dmi_info.h @@ -0,0 +1,240 @@ + /***************************************************************************** + * + * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#define AMD_FSP_DMI_HOB_GUID {0x4118FC0E, 0x353D, 0x4726, { 0x97, 0xC0, 0x53, 0xCD, 0x92, 0xB6, 0x49, 0x25}} + +// Our ACPI HOB max payload, accounting for the size of the HOB header as well as the information structure +#define HOB_MAX_SIZE 0xFFF8 +#define HOB_GUID_EXTENSION_SIZE (HOB_MAX_SIZE - sizeof (EFI_HOB_GUID_TYPE)) + +#define MAX_SOCKETS_SUPPORTED 4 ///< Max number of sockets in system +#define MAX_CHANNELS_PER_SOCKET 12 ///< Max Channels per sockets +#define MAX_DIMMS_PER_CHANNEL 2 ///< Max DIMMs on a memory channel (independent of platform) + +/// DMI Type 16 offset 04h - Location +typedef enum { + OtherLocation = 0x01, ///< Assign 01 to Other + UnknownLocation, ///< Assign 02 to Unknown + SystemboardOrMotherboard, ///< Assign 03 to systemboard or motherboard + IsaAddonCard, ///< Assign 04 to ISA add-on card + EisaAddonCard, ///< Assign 05 to EISA add-on card + PciAddonCard, ///< Assign 06 to PCI add-on card + McaAddonCard, ///< Assign 07 to MCA add-on card + PcmciaAddonCard, ///< Assign 08 to PCMCIA add-on card + ProprietaryAddonCard, ///< Assign 09 to proprietary add-on card + NuBus, ///< Assign 0A to NuBus + Pc98C20AddonCard, ///< Assign 0A0 to PC-98/C20 add-on card + Pc98C24AddonCard, ///< Assign 0A1 to PC-98/C24 add-on card + Pc98EAddoncard, ///< Assign 0A2 to PC-98/E add-on card + Pc98LocalBusAddonCard ///< Assign 0A3 to PC-98/Local bus add-on card +} DMI_T16_LOCATION; + +/// DMI Type 16 offset 05h - Memory Error Correction +typedef enum { + OtherUse = 0x01, ///< Assign 01 to Other + UnknownUse, ///< Assign 02 to Unknown + SystemMemory, ///< Assign 03 to system memory + VideoMemory, ///< Assign 04 to video memory + FlashMemory, ///< Assign 05 to flash memory + NonvolatileRam, ///< Assign 06 to non-volatile RAM + CacheMemory ///< Assign 07 to cache memory +} DMI_T16_USE; + +/// DMI Type 16 offset 07h - Maximum Capacity +typedef enum { + Dmi16OtherErrCorrection = 0x01, ///< Assign 01 to Other + Dmi16UnknownErrCorrection, ///< Assign 02 to Unknown + Dmi16NoneErrCorrection, ///< Assign 03 to None + Dmi16Parity, ///< Assign 04 to parity + Dmi16SingleBitEcc, ///< Assign 05 to Single-bit ECC + Dmi16MultiBitEcc, ///< Assign 06 to Multi-bit ECC + Dmi16Crc ///< Assign 07 to CRC +} DMI_T16_ERROR_CORRECTION; + +/// DMI Type 16 - Physical Memory Array +typedef struct { + OUT DMI_T16_LOCATION Location; ///< The physical location of the Memory Array, + ///< whether on the system board or an add-in board. + OUT DMI_T16_USE Use; ///< Identifies the function for which the array + ///< is used. + OUT DMI_T16_ERROR_CORRECTION MemoryErrorCorrection; ///< The primary hardware error correction or + ///< detection method supported by this memory array. + OUT UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available + ///< for memory devices in this array. +} TYPE16_DMI_INFO; + +/// DMI Type 17 offset 0Eh - Form Factor +typedef enum { + OtherFormFactor = 0x01, ///< Assign 01 to Other + UnknowFormFactor, ///< Assign 02 to Unknown + SimmFormFactor, ///< Assign 03 to SIMM + SipFormFactor, ///< Assign 04 to SIP + ChipFormFactor, ///< Assign 05 to Chip + DipFormFactor, ///< Assign 06 to DIP + ZipFormFactor, ///< Assign 07 to ZIP + ProprietaryCardFormFactor, ///< Assign 08 to Proprietary Card + DimmFormFactorFormFactor, ///< Assign 09 to DIMM + TsopFormFactor, ///< Assign 10 to TSOP + RowOfChipsFormFactor, ///< Assign 11 to Row of chips + RimmFormFactor, ///< Assign 12 to RIMM + SodimmFormFactor, ///< Assign 13 to SODIMM + SrimmFormFactor, ///< Assign 14 to SRIMM + FbDimmFormFactor ///< Assign 15 to FB-DIMM +} DMI_T17_FORM_FACTOR; + +/// DMI Type 17 offset 12h - Memory Type +typedef enum { + OtherMemType = 0x01, ///< Assign 01 to Other + UnknownMemType, ///< Assign 02 to Unknown + DramMemType, ///< Assign 03 to DRAM + EdramMemType, ///< Assign 04 to EDRAM + VramMemType, ///< Assign 05 to VRAM + SramMemType, ///< Assign 06 to SRAM + RamMemType, ///< Assign 07 to RAM + RomMemType, ///< Assign 08 to ROM + FlashMemType, ///< Assign 09 to Flash + EepromMemType, ///< Assign 10 to EEPROM + FepromMemType, ///< Assign 11 to FEPROM + EpromMemType, ///< Assign 12 to EPROM + CdramMemType, ///< Assign 13 to CDRAM + ThreeDramMemType, ///< Assign 14 to 3DRAM + SdramMemType, ///< Assign 15 to SDRAM + SgramMemType, ///< Assign 16 to SGRAM + RdramMemType, ///< Assign 17 to RDRAM + DdrMemType, ///< Assign 18 to DDR + Ddr2MemType, ///< Assign 19 to DDR2 + Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM + Ddr3MemType = 0x18, ///< Assign 24 to DDR3 + Fbd2MemType, ///< Assign 25 to FBD2 + Ddr4MemType, ///< Assign 26 to DDR4 + LpDdrMemType, ///< Assign 27 to LPDDR + LpDdr2MemType, ///< Assign 28 to LPDDR2 + LpDdr3MemType, ///< Assign 29 to LPDDR3 + LpDdr4MemType, ///< Assign 30 to LPDDR4 + LogicalNonVolatileDeviceMemType, ///< Assign 31 to Logical non-volatile device + HbmMemType, ///< Assign 32 to HBM + Hbm2MemType, ///< Assign 33 to HBM2 + Ddr5MemType, ///< Assign 34 to DDR5 + LpDdr5MemType, ///< Assign 35 to LPDDR5 + Hbm3MemType, ///< Assign 36 to HBM3 +} DMI_T17_MEMORY_TYPE; + +/// DMI Type 17 offset 13h - Type Detail +typedef struct { + OUT UINT16 Reserved1:1; ///< Reserved + OUT UINT16 Other:1; ///< Other + OUT UINT16 Unknown:1; ///< Unknown + OUT UINT16 FastPaged:1; ///< Fast-Paged + OUT UINT16 StaticColumn:1; ///< Static column + OUT UINT16 PseudoStatic:1; ///< Pseudo-static + OUT UINT16 Rambus:1; ///< RAMBUS + OUT UINT16 Synchronous:1; ///< Synchronous + OUT UINT16 Cmos:1; ///< CMOS + OUT UINT16 Edo:1; ///< EDO + OUT UINT16 WindowDram:1; ///< Window DRAM + OUT UINT16 CacheDram:1; ///< Cache Dram + OUT UINT16 NonVolatile:1; ///< Non-volatile + OUT UINT16 Registered:1; ///< Registered (Buffered) + OUT UINT16 Unbuffered:1; ///< Unbuffered (Unregistered) + OUT UINT16 LRDIMM:1; ///< LRDIMM +} DMI_T17_TYPE_DETAIL; + +/// DMI Type 17 offset 28h - Memory Technology +typedef enum { + OtherType = 0x01, ///< Assign 01 to Other + UnknownType = 0x02, ///< Assign 02 to Unknown + DramType = 0x03, ///< Assign 03 to DRAM + NvDimmNType = 0x04, ///< Assign 04 to NVDIMM-N + NvDimmFType = 0x05, ///< Assign 05 to NVDIMM-F + NvDimmPType = 0x06, ///< Assign 06 to NVDIMM-P + IntelPersistentMemoryType = 0x07, ///< Assign 07 to Intel persistent memory +} DMI_T17_MEMORY_TECHNOLOGY; + +/// DMI Type 17 offset 29h - Memory Operating Mode Capability +typedef struct { + OUT UINT16 Reserved1:1; ///< Reserved, set to 0 + OUT UINT16 Other:1; ///< Other + OUT UINT16 Unknown:1; ///< Unknown + OUT UINT16 VolatileMemory:1; ///< Volatile memory + OUT UINT16 ByteAccessiblePersistentMemory:1; ///< Byte-accessible persistent memory + OUT UINT16 BlockAccessiblePersistentMemory:1; ///< Block-accessible persistent memory + OUT UINT16 Reserved2:10; ///< Reserved, set to 0 +} DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY; + +typedef union { + DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY AsBitmap; + UINT16 AsUint16; +} DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY_VAR; + +/// DMI Type 17 - Memory Device +typedef struct { + OUT UINT16 Handle; ///< The temporary handle, or instance number, associated with the structure + OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. + OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device. + OUT UINT16 MemorySize; ///< The size of the memory device. + OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device. + OUT UINT8 DeviceSet; ///< Identifies when the Memory Device is one of a set of + ///< Memory Devices that must be populated with all devices of + ///< the same type and size, and the set to which this device belongs. + OUT CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. + OUT CHAR8 BankLocator[13]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. + OUT DMI_T17_MEMORY_TYPE MemoryType; ///< The type of memory used in this device. + OUT DMI_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type + OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). + OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. + OUT CHAR8 SerialNumber[9]; ///< Serial Number. + OUT CHAR8 PartNumber[21]; ///< Part Number. + OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. + OUT UINT32 ExtSize; ///< Extended Size. + OUT UINT16 ConfigSpeed; ///< Configured memory clock speed + OUT UINT16 MinimumVoltage; ///< Minimum operating voltage for this device, in millivolts + OUT UINT16 MaximumVoltage; ///< Maximum operating voltage for this device, in millivolts + OUT UINT16 ConfiguredVoltage; ///< Configured voltage for this device, in millivolts + // SMBIOS 3.2 + OUT UINT8 MemoryTechnology; ///< Memory technology type for this memory device + OUT DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY_VAR MemoryOperatingModeCapability; ///< The operating modes supported by this memory device + OUT CHAR8 FirmwareVersion[10]; ///< String number for the firmware version of this memory device + OUT UINT16 ModuleManufacturerId; ///< The two-byte module manufacturer ID found in the SPD of this memory device; LSB first. + OUT UINT16 ModuleProductId; ///< The two-byte module product ID found in the SPD of this memory device; LSB first + OUT UINT16 MemorySubsystemControllerManufacturerId; //< The two-byte memory subsystem controller manufacturer ID found in the SPD of this memory device; LSB first + OUT UINT16 MemorySubsystemControllerProductId; //< The two-byte memory subsystem controller product ID found in the SPD of this memory device; LSB first + OUT UINT64 NonvolatileSize; ///< Size of the Non-volatile portion of the memory device in Bytes, if any. + OUT UINT64 VolatileSize; ///< Size of the Volatile portion of the memory device in Bytes, if any. + OUT UINT64 CacheSize; ///< Size of the Cache portion of the memory device in Bytes, if any. + OUT UINT64 LogicalSize; ///< Size of the Logical memory device in Bytes. + // SMBIOS 3.3 + OUT UINT32 ExtendedSpeed; ///< Extended Speed + OUT UINT32 ExtendedConfiguredMemorySpeed; ///< Extended Configured memory speed +} __packed TYPE17_DMI_INFO; + +/// Collection of pointers to the DMI records +typedef struct { + OUT TYPE16_DMI_INFO T16; ///< Type 16 struc + OUT TYPE17_DMI_INFO T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc +} DMI_INFO; -- To view, visit https://review.coreboot.org/c/coreboot/+/76107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e0109af51b78360f7038b20a2975aceb721a7d5 Gerrit-Change-Number: 76107 Gerrit-PatchSet: 1 Gerrit-Owner: Konrad Adamczyk <konrada(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/emulation: Enhance ROM_SIZE
by Maximilian Brune (Code Review) 27 Jun '23

27 Jun '23

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76106?usp=email ) Change subject: mb/emulation: Enhance ROM_SIZE ...................................................................... mb/emulation: Enhance ROM_SIZE Some payloads tend to need bigger space than what our current defaults allow. Linuxboot is a good example. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I7029ca3360d936b67ff9873fa13cf9cc60445e56 --- M src/mainboard/emulation/qemu-aarch64/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-riscv/Kconfig 3 files changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/76106/1 diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig index 64d7d78..f7f2250 100644 --- a/src/mainboard/emulation/qemu-aarch64/Kconfig +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig @@ -12,7 +12,7 @@ select ARCH_ROMSTAGE_ARMV8_64 select ARCH_RAMSTAGE_ARMV8_64 select ARM64_USE_ARCH_TIMER - select BOARD_ROMSIZE_KB_4096 + select BOARD_ROMSIZE_KB_16384 select BOOTBLOCK_CUSTOM select BOOT_DEVICE_NOT_SPI_FLASH select DRIVERS_UART_PL011 diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 3105069..489fd07 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -8,8 +8,7 @@ select HAVE_OPTION_TABLE # select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_2048 if !VBOOT - select BOARD_ROMSIZE_KB_16384 if VBOOT + select BOARD_ROMSIZE_KB_16384 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT if !CHROMEOS select MEMORY_MAPPED_TPM diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 0af309a..091c432 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -24,7 +24,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_UCB_RISCV - select BOARD_ROMSIZE_KB_4096 + select BOARD_ROMSIZE_KB_16384 select BOOT_DEVICE_NOT_SPI_FLASH select MISSING_BOARD_RESET select DRIVERS_UART_8250MEM -- To view, visit https://review.coreboot.org/c/coreboot/+/76106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7029ca3360d936b67ff9873fa13cf9cc60445e56 Gerrit-Change-Number: 76106 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: mb/bytedance: Add 2 SPR sockets server board bd_egs
by Nico Huber (Code Review) 27 Jun '23

27 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Elyes Haouas, Felix Held, Felix Singer, Jonathan Zhang, Nill Ge, Patrick Rudolph, Paul Menzel, TangYiwei, niehaitao(a)bytedance.com. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75722?usp=email ) Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs ...................................................................... Patch Set 13: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d Gerrit-Change-Number: 75722 Gerrit-PatchSet: 13 Gerrit-Owner: TangYiwei Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: niehaitao(a)bytedance.com Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: laykong <lay.kong(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: niehaitao(a)bytedance.com Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 27 Jun 2023 14:12:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/intel/microcode: Have CPU microcode per CPUID into CBFS
by Kapil Porwal (Code Review) 27 Jun '23

27 Jun '23

Attention is currently required from: Arthur Heymans, Himanshu Sahdev, Julius Werner, Lean Sheng Tan, Rizwan Qureshi, Subrata Banik, Tarun Tuli, Wonkyu Kim, Yu-Ping Wu. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75357?usp=email ) Change subject: cpu/intel/microcode: Have CPU microcode per CPUID into CBFS ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75357?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7db73335ffa25399869cfb0d59129ee118f1012 Gerrit-Change-Number: 75357 Gerrit-PatchSet: 18 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 27 Jun 2023 13:29:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: intelblocks/pep: Send All Monitor Off/On command only in FWCM case
by Kapil Porwal (Code Review) 27 Jun '23

27 Jun '23

Attention is currently required from: Balaji Manigandan, Felix Held, Felix Singer, Hannah Williams, Jamie Ryu, Paul Menzel, Subrata Banik, Tarun Tuli, Usha P, Utkarsh H Patel, Vikrant Jadeja. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75717?usp=email ) Change subject: intelblocks/pep: Send All Monitor Off/On command only in FWCM case ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I110fb971846f110e7d93a524ceda3bf4bfc15c13 Gerrit-Change-Number: 75717 Gerrit-PatchSet: 9 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: Vikrant Jadeja Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Vikrant Jadeja Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 27 Jun 2023 13:24:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex: Enable Bluetooth offload for soundwire audio
by Kapil Porwal (Code Review) 27 Jun '23

27 Jun '23

Attention is currently required from: Jakub Czapiga, Subrata Banik, Tarun Tuli, Uday Bhat. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75924?usp=email ) Change subject: mb/google/rex: Enable Bluetooth offload for soundwire audio ...................................................................... Patch Set 10: (1 comment) Patchset: PS9: > This is mentioned as SSP1 in the commit message ... SSP1 sounds better. Ack. > Related OS changes are under review Got it -- To view, visit https://review.coreboot.org/c/coreboot/+/75924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99df78787d9f54c91bcedf6f70352890a715cdb3 Gerrit-Change-Number: 75924 Gerrit-PatchSet: 10 Gerrit-Owner: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Comment-Date: Tue, 27 Jun 2023 12:39:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/{brasswell, denverton_ns}: Remove NOOP second SSDT
by Arthur Heymans (Code Review) 27 Jun '23

27 Jun '23

Attention is currently required from: Jeff Daly, Vanessa Eusebio. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76130?usp=email ) Change subject: soc/intel/{brasswell, denverton_ns}: Remove NOOP second SSDT ...................................................................... soc/intel/{brasswell, denverton_ns}: Remove NOOP second SSDT A second SSDT is never added as only NOOP weak functions exist. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Icbe032cb133416caf7d48e00e070cfc26419fcfb --- M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/fadt.c D src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/braswell/placeholders.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/denverton_ns/lpc.c 8 files changed, 0 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/76130/1 diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 6423ebe..765f13e 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -12,7 +12,6 @@ #include <cpu/x86/smm.h> #include <device/pci.h> #include <drivers/intel/gma/opregion.h> -#include <soc/acpi.h> #include <soc/device_nvs.h> #include <soc/gfx.h> #include <soc/iomap.h> @@ -317,29 +316,3 @@ /* Add a method to notify processor nodes */ acpigen_write_processor_cnot(pattrs->num_cpus); } - -unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, - struct acpi_rsdp *rsdp) -{ - acpi_header_t *ssdt2 = (acpi_header_t *)current; - memset(ssdt2, 0, sizeof(acpi_header_t)); - acpi_create_serialio_ssdt(ssdt2); - if (ssdt2->length) { - current += ssdt2->length; - acpi_add_table(rsdp, ssdt2); - printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n", ssdt2, ssdt2->length); - current = acpi_align_current(current); - - } else { - ssdt2 = NULL; - printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); - } - - printk(BIOS_DEBUG, "current = %lx\n", current); - - return current; -} - -__weak void acpi_create_serialio_ssdt(acpi_header_t *ssdt) -{ -} diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c index ac1653d..e4e225e 100644 --- a/src/soc/intel/braswell/fadt.c +++ b/src/soc/intel/braswell/fadt.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <soc/acpi.h> #include <soc/iomap.h> #include <soc/pm.h> diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h deleted file mode 100644 index fa4c804..0000000 --- a/src/soc/intel/braswell/include/soc/acpi.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_ACPI_H_ -#define _SOC_ACPI_H_ - -#include <acpi/acpi.h> - -void acpi_create_serialio_ssdt(acpi_header_t *ssdt); -unsigned long southcluster_write_acpi_tables(const struct device *device, - unsigned long current, struct acpi_rsdp *rsdp); - -#endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/braswell/placeholders.c b/src/soc/intel/braswell/placeholders.c index 15514f9..160dfb6 100644 --- a/src/soc/intel/braswell/placeholders.c +++ b/src/soc/intel/braswell/placeholders.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/pci_rom.h> -#include <soc/acpi.h> /* Rmodules don't like weak symbols. */ u32 map_oprom_vendev(u32 vendev) { return vendev; } diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index a0df97c..fbc02be 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -14,7 +14,6 @@ #include <pc80/isa-dma.h> #include <pc80/i8254.h> #include <pc80/i8259.h> -#include <soc/acpi.h> #include <soc/iomap.h> #include <soc/irq.h> #include <soc/lpc.h> @@ -524,7 +523,6 @@ static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, - .write_acpi_tables = southcluster_write_acpi_tables, .init = sc_init, .enable = southcluster_enable_dev, .scan_bus = scan_static_bus, diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index feb6d6f..4dc9dd8 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -146,35 +146,6 @@ return MP_IRQ_POLARITY_HIGH; } -unsigned long southcluster_write_acpi_tables(const struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - acpi_header_t *ssdt2; - - current = (ALIGN_UP(current, 16)); - - ssdt2 = (acpi_header_t *)current; - memset(ssdt2, 0, sizeof(acpi_header_t)); - acpi_create_serialio_ssdt(ssdt2); - if (ssdt2->length) { - current += ssdt2->length; - acpi_add_table(rsdp, ssdt2); - printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n", ssdt2, - ssdt2->length); - current = (ALIGN_UP(current, 16)); - } else { - ssdt2 = NULL; - printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); - } - - printk(BIOS_DEBUG, "current = %lx\n", current); - - return current; -} - -__weak void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} - static unsigned long acpi_fill_dmar(unsigned long current) { uint64_t vtbar; diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index 41a60d0..5e7f0f3 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -5,11 +5,7 @@ #include <acpi/acpi.h> -void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long acpi_madt_irq_overrides(unsigned long current); -unsigned long southcluster_write_acpi_tables(const struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp); unsigned long systemagent_write_acpi_tables(const struct device *dev, unsigned long start, struct acpi_rsdp *const rsdp); diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 7ebca1e..4885024 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -518,9 +518,6 @@ static struct device_operations device_ops = { .read_resources = lpc_read_resources, .set_resources = pci_dev_set_resources, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = southcluster_write_acpi_tables, -#endif .enable_resources = lpc_enable_resources, .init = lpc_init, .enable = southcluster_enable_dev, -- To view, visit https://review.coreboot.org/c/coreboot/+/76130?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbe032cb133416caf7d48e00e070cfc26419fcfb Gerrit-Change-Number: 76130 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: sb/intel/lynxpoint: Don't generate second SSDT
by Arthur Heymans (Code Review) 27 Jun '23

27 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76129?usp=email ) Change subject: sb/intel/lynxpoint: Don't generate second SSDT ...................................................................... sb/intel/lynxpoint: Don't generate second SSDT Move the entries in SSDT to acpi_fill_ssdt(). There is need for a separate table. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ie23d5b5b967de162ea9ac60a64bc92d0b3bee08e --- M src/southbridge/intel/lynxpoint/Makefile.inc D src/southbridge/intel/lynxpoint/acpi.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.h 4 files changed, 12 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/76129/1 diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 5088d8b..c09beb6 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -23,7 +23,6 @@ endif ramstage-y += me_status.c -ramstage-y += acpi.c ramstage-$(CONFIG_ELOG) += elog.c diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c deleted file mode 100644 index aa6e650..0000000 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> -#include <acpi/acpigen.h> -#include <string.h> -#include <version.h> -#include <soc/nvs.h> - -#include "pch.h" - -static void acpi_create_serialio_ssdt_entry(int id, struct global_nvs *gnvs) -{ - char sio_name[5] = {}; - snprintf(sio_name, sizeof(sio_name), "S%1uEN", id); - acpigen_write_name_byte(sio_name, gnvs->s0b[id] ? 1 : 0); -} - -void acpi_create_serialio_ssdt(acpi_header_t *ssdt) -{ - unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t); - struct global_nvs *gnvs = acpi_get_gnvs(); - int id; - - if (!gnvs) - return; - - /* Fill the SSDT header */ - memset((void *)ssdt, 0, sizeof(acpi_header_t)); - memcpy(&ssdt->signature, "SSDT", 4); - ssdt->revision = get_acpi_table_revision(SSDT); - memcpy(&ssdt->oem_id, OEM_ID, 6); - memcpy(&ssdt->oem_table_id, "SERIALIO", 8); - ssdt->oem_revision = 43; - memcpy(&ssdt->asl_compiler_id, ASLC, 4); - ssdt->asl_compiler_revision = asl_revision; - ssdt->length = sizeof(acpi_header_t); - acpigen_set_current((char *)current); - - /* Fill the SSDT with an entry for each SerialIO device */ - for (id = 0; id < 8; id++) - acpi_create_serialio_ssdt_entry(id, gnvs); - - /* (Re)calculate length and checksum. */ - current = (unsigned long)acpigen_get_current(); - ssdt->length = current - (unsigned long)ssdt; - ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); -} diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 67f1e54..680622b 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -752,33 +752,21 @@ return "LPCB"; } +static void acpi_create_serialio_ssdt_entry(int id, struct global_nvs *gnvs) +{ + char sio_name[5] = {}; + snprintf(sio_name, sizeof(sio_name), "S%1uEN", id); + acpigen_write_name_byte(sio_name, gnvs->s0b[id] ? 1 : 0); +} + static void southbridge_fill_ssdt(const struct device *dev) { intel_acpi_gen_def_acpi_pirq(dev); -} - -static unsigned long southbridge_write_acpi_tables(const struct device *device, - unsigned long start, - struct acpi_rsdp *rsdp) -{ - unsigned long current; - - current = start; - - /* Align ACPI tables to 16byte */ - current = acpi_align_current(current); - - if (pch_is_lp()) { - printk(BIOS_DEBUG, "ACPI: * SSDT2\n"); - acpi_header_t *ssdt = (acpi_header_t *)current; - acpi_create_serialio_ssdt(ssdt); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - current = acpi_align_current(current); - } - - printk(BIOS_DEBUG, "current = %lx\n", current); - return current; + acpigen_write_scope("\\"); + /* Fill the SSDT with an entry for each SerialIO device */ + for (id = 0; id < 8; id++) + acpi_create_serialio_ssdt_entry(id, gnvs); + acpigen_write_scope_end(); } static void lpc_final(struct device *dev) @@ -798,7 +786,6 @@ .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, - .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, .final = lpc_final, .enable = pch_lpc_enable, diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 07f4b9d..1162214 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -157,7 +157,6 @@ void pch_enable(struct device *dev); void pch_disable_devfn(struct device *dev); void pch_log_state(void); -void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void enable_usb_bar(void); void early_pch_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/76129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie23d5b5b967de162ea9ac60a64bc92d0b3bee08e Gerrit-Change-Number: 76129 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: acpi: Move HPET generation to a common location
by Arthur Heymans (Code Review) 27 Jun '23

27 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jeff Daly, Lance Zhao, Matt DeVillier, Raul Rangel, Tim Wawrzynczak, Vanessa Eusebio. Hello Felix Held, Fred Reitberger, Jason Glenesk, Jeff Daly, Lance Zhao, Matt DeVillier, Raul Rangel, Tim Wawrzynczak, Vanessa Eusebio, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76128?usp=email to look at the new patch set (#2). Change subject: acpi: Move HPET generation to a common location ...................................................................... acpi: Move HPET generation to a common location HPET is usually a feature of the hardware that needs to no runtime to check whether it is present or it is typically unconditionally enabled. This means a simple Kconfig option to generate the ACPI tables is suffices, which allows reduction of boilerplate. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I38b9962a8d568267356256a3edc51348b9417e20 --- M src/acpi/Kconfig M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/amd/common/block/acpi/Kconfig M src/soc/amd/common/block/acpi/Makefile.inc D src/soc/amd/common/block/acpi/tables.c M src/soc/amd/common/block/include/amdblocks/acpi.h M src/soc/amd/common/block/lpc/lpc.c M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/pch/Kconfig M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/acpi.c M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82371eb/Kconfig M src/southbridge/intel/i82371eb/isa.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/lpc.c 35 files changed, 31 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/76128/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76128?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38b9962a8d568267356256a3edc51348b9417e20 Gerrit-Change-Number: 76128 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: soc/amd/common/block/acpi/ivrs: fix missing IOAPIC[1] error
by Fred Reitberger (Code Review) 27 Jun '23

27 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Jason Glenesk, Martin L Roth, Matt DeVillier, Raul Rangel. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76117?usp=email ) Change subject: soc/amd/common/block/acpi/ivrs: fix missing IOAPIC[1] error ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/76117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id88f17d68ba5accef6561837478828bd3d24baa5 Gerrit-Change-Number: 76117 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 27 Jun 2023 11:37:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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