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[M] Change in coreboot[master]: acpi: Move HPET generation to a common location
by Arthur Heymans (Code Review) 27 Jun '23

27 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76128?usp=email ) Change subject: acpi: Move HPET generation to a common location ...................................................................... acpi: Move HPET generation to a common location HPET is usually a feature of the hardware that needs to no runtime to check whether it is present or it is typically unconditionally enabled. This means a simple Kconfig option to generate the ACPI tables is suffices, which allows reduction of boilerplate. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I38b9962a8d568267356256a3edc51348b9417e20 --- M src/acpi/Kconfig M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/amd/common/block/acpi/Kconfig M src/soc/amd/common/block/acpi/Makefile.inc D src/soc/amd/common/block/acpi/tables.c M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/pch/Kconfig M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/acpi.c M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82371eb/Kconfig M src/southbridge/intel/i82371eb/isa.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/lpc.c 33 files changed, 31 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/76128/1 diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index a45a68c..a766319 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -68,3 +68,10 @@ depends on HAVE_ACPI_TABLES help Selected by platforms that support and fill Intel Low Power Idle Table. + +config ACPI_HPET + bool + default n + depends on HAVE_ACPI_TABLES + help + Select this on platforms that feature a HPET. diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 5a571d7..f3fe232 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1034,12 +1034,13 @@ } /* http://www.intel.com/hardwaredesign/hpetspec_1.pdf */ -static void acpi_create_hpet(acpi_hpet_t *hpet) +static void acpi_create_hpet(acpi_header_t *header, void *arg) { - acpi_header_t *header = &(hpet->header); - acpi_addr_t *addr = &(hpet->addr); + if (!CONFIG(ACPI_HPET)) + return; - memset((void *)hpet, 0, sizeof(acpi_hpet_t)); + acpi_hpet_t *hpet = (acpi_hpet_t *)header; + acpi_addr_t *addr = &(hpet->addr); if (!header) return; @@ -1064,8 +1065,6 @@ hpet->id = read32p(HPET_BASE_ADDRESS); hpet->number = 0; hpet->min_tick = CONFIG_HPET_MIN_TICKS; - - header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } /* @@ -1356,25 +1355,6 @@ header->checksum = acpi_checksum((void *)crat, header->length); } -unsigned long acpi_write_hpet(const struct device *device, unsigned long current, - acpi_rsdp_t *rsdp) -{ - acpi_hpet_t *hpet; - - /* - * We explicitly add these tables later on: - */ - printk(BIOS_DEBUG, "ACPI: * HPET\n"); - - hpet = (acpi_hpet_t *)current; - current += sizeof(acpi_hpet_t); - current = ALIGN_UP(current, 16); - acpi_create_hpet(hpet); - acpi_add_table(rsdp, hpet); - - return current; -} - static void acpi_create_dbg2(acpi_dbg2_header_t *dbg2, int port_type, int port_subtype, acpi_addr_t *address, uint32_t address_size, @@ -1927,6 +1907,7 @@ { acpi_create_lpit, NULL, sizeof(acpi_lpit_t) }, { acpi_create_madt, NULL, sizeof(acpi_header_t) }, { acpi_create_bert, NULL, sizeof(acpi_bert_t) }, + { acpi_create_hpet, NULL, sizeof(acpi_hpet_t) }, }; current = start; diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index d3f209a..3b953e0 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1418,9 +1418,6 @@ unsigned long (*acpi_fill_crat)(struct acpi_crat_header *crat_struct, unsigned long current)); -unsigned long acpi_write_hpet(const struct device *device, unsigned long start, - acpi_rsdp_t *rsdp); - /* cpu/intel/speedstep/acpi.c */ void generate_cpu_entries(const struct device *device); diff --git a/src/soc/amd/common/block/acpi/Kconfig b/src/soc/amd/common/block/acpi/Kconfig index 9355f7d..df4f61b 100644 --- a/src/soc/amd/common/block/acpi/Kconfig +++ b/src/soc/amd/common/block/acpi/Kconfig @@ -5,6 +5,7 @@ select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC select ACPI_CUSTOM_MADT + select ACPI_HPET help Select this option to use the AcpiMmio ACPI registers. diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index a0d9290..a9688a7 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -5,7 +5,6 @@ smm-y += acpi.c ramstage-y += pm_state.c -ramstage-y += tables.c ramstage-$(CONFIG_ACPI_BERT) += bert.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_ALIB) += alib.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_CPPC) += cppc.c diff --git a/src/soc/amd/common/block/acpi/tables.c b/src/soc/amd/common/block/acpi/tables.c deleted file mode 100644 index bda283a..0000000 --- a/src/soc/amd/common/block/acpi/tables.c +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -#include <acpi/acpigen.h> -#include <amdblocks/acpi.h> -#include <device/device.h> -#include <types.h> - -unsigned long southbridge_write_acpi_tables(const struct device *device, - unsigned long current, - struct acpi_rsdp *rsdp) -{ - return acpi_write_hpet(device, current, rsdp); -} diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 958af34..7e5267e 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -9,6 +9,7 @@ def_bool y select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC + select ACPI_HPET select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 1afea59..8beee73 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -476,7 +476,6 @@ static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, - .write_acpi_tables = acpi_write_hpet, .init = sc_init, .enable = southcluster_enable_dev, .scan_bus = scan_static_bus, diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index f618118..a48397d 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -115,6 +115,9 @@ Enable this to disable the HPET support Solves the Linux MP-BIOS bug timer not connected. +config ACPI_HPET + default y if !DISABLE_HPET + config USE_GOOGLE_FSP bool help diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index a278e55..6423ebe 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -321,14 +321,7 @@ unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { - acpi_header_t *ssdt2; - - if (!CONFIG(DISABLE_HPET)) { - current = acpi_write_hpet(device, current, rsdp); - current = acpi_align_current(current); - } - - ssdt2 = (acpi_header_t *)current; + acpi_header_t *ssdt2 = (acpi_header_t *)current; memset(ssdt2, 0, sizeof(acpi_header_t)); acpi_create_serialio_ssdt(ssdt2); if (ssdt2->length) { diff --git a/src/soc/intel/broadwell/pch/Kconfig b/src/soc/intel/broadwell/pch/Kconfig index bd1bea5..90aa02b 100644 --- a/src/soc/intel/broadwell/pch/Kconfig +++ b/src/soc/intel/broadwell/pch/Kconfig @@ -6,6 +6,7 @@ def_bool y select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC + select ACPI_HPET select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 9aaca21..c568f90 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -605,7 +605,6 @@ PCH_DEV_UART1 : PCH_DEV_UART0, ACPI_ACCESS_SIZE_DWORD_ACCESS); } - return acpi_write_hpet(device, current, rsdp); } static struct device_operations device_ops = { diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index c750e7e..0264140 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -4,6 +4,7 @@ select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC if !SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID select ACPI_CUSTOM_MADT + select ACPI_HPET bool help Intel Processor common code for ACPI diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 2c27b15..6886063 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -150,8 +150,6 @@ uart_get_device(), ACPI_ACCESS_SIZE_DWORD_ACCESS); } - - return acpi_write_hpet(device, current, rsdp); } __weak diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 0c4780b..a4d5704 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -94,7 +94,7 @@ */ void pch_misc_init(void); /* - * Calls acpi_write_hpet which creates and fills HPET table and + * Calls acpi_write_dbg2_pci_uart which created DBG2 table and * adds it to the RSDT (and XSDT) structure. */ unsigned long southbridge_write_acpi_tables(const struct device *device, diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index dcf9a5f..080ec26 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -35,6 +35,7 @@ select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_PMC select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_HPET select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 6ddcc08..feb6d6f 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -152,7 +152,6 @@ { acpi_header_t *ssdt2; - current = acpi_write_hpet(device, current, rsdp); current = (ALIGN_UP(current, 16)); ssdt2 = (acpi_header_t *)current; diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 6a3d61d..b0873da 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -13,6 +13,7 @@ select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC select ACPI_CUSTOM_MADT + select ACPI_HPET select HAVE_USBDEBUG_OPTIONS select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 0a4e038..821f6b1 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -342,9 +342,6 @@ .read_resources = hudson_lpc_read_resources, .set_resources = hudson_lpc_set_resources, .enable_resources = hudson_lpc_enable_resources, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = acpi_write_hpet, -#endif .init = lpc_init, .final = lpc_final, .scan_bus = scan_static_bus, diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 5ba913d..b5aa4d7 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -12,6 +12,7 @@ def_bool y select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC + select ACPI_HPET select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0cf7b9c..cc168b7 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -662,7 +662,6 @@ .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .init = lpc_init, diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index 3f84668..33384fc 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -1,6 +1,7 @@ config SOUTHBRIDGE_INTEL_I82371EB select ACPI_COMMON_MADT_IOAPIC if SMP select ACPI_COMMON_MADT_LAPIC if SMP + select ACPI_HPET select ACPI_NO_CUSTOM_MADT select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 7d86e8a..ad31139 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -106,7 +106,6 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, #if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt = generate_cpu_entries, #endif .init = isa_init, diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 2467e39..c7414e6 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -4,6 +4,7 @@ bool select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC + select ACPI_HPET select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 28cde3e..cff84a8 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -433,7 +433,6 @@ .read_resources = i82801gx_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .init = lpc_init, diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index fb33474..97b4358 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -4,6 +4,7 @@ bool select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC + select ACPI_HPET select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index d897130..eabcf1c 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -465,7 +465,6 @@ .read_resources = i82801ix_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .init = lpc_init, diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 3f0ab10..5a132ef 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -4,6 +4,7 @@ bool select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC + select ACPI_HPET select ACPI_INTEL_HARDWARE_SLEEP_VALUES select AZALIA_PLUGIN_SUPPORT select HAVE_POWER_STATE_AFTER_FAILURE diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index e93502f..7810d2d 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -468,7 +468,6 @@ .read_resources = i82801jx_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .init = lpc_init, diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index adc3842..e6d16c3 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -9,6 +9,7 @@ def_bool y select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC + select ACPI_HPET select ACPI_INTEL_HARDWARE_SLEEP_VALUES select AZALIA_PLUGIN_SUPPORT select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 7d85883..cee8871 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -538,7 +538,6 @@ .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, - .write_acpi_tables = acpi_write_hpet, .init = lpc_init, .final = lpc_final, .enable = pch_lpc_enable, diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 0804298..a7109b7 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -9,6 +9,7 @@ def_bool y select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC + select ACPI_HPET select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index e44d9a8..67f1e54 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -768,13 +768,6 @@ /* Align ACPI tables to 16byte */ current = acpi_align_current(current); - /* - * We explicitly add these tables later on: - */ - current = acpi_write_hpet(device, current, rsdp); - - current = acpi_align_current(current); - if (pch_is_lp()) { printk(BIOS_DEBUG, "ACPI: * SSDT2\n"); acpi_header_t *ssdt = (acpi_header_t *)current; -- To view, visit https://review.coreboot.org/c/coreboot/+/76128?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38b9962a8d568267356256a3edc51348b9417e20 Gerrit-Change-Number: 76128 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: acpi: Add SPCR table
by Nico Huber (Code Review) 27 Jun '23

27 Jun '23

Attention is currently required from: Arthur Heymans, Benjamin Doron, Lance Zhao, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75685?usp=email ) Change subject: acpi: Add SPCR table ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64e624c17a27b9215a8ba83bd6cbb2c0a7aa1dfc Gerrit-Change-Number: 75685 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 27 Jun 2023 10:45:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: lib: Support localized text of memory_training_desc in ux_locales.c
by Hsuan-ting Chen (Code Review) 27 Jun '23

27 Jun '23

Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75330?usp=email ) Change subject: lib: Support localized text of memory_training_desc in ux_locales.c ...................................................................... Patch Set 9: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75330/comment/3a3668ff_5facddb4 : PS9, Line 13: The preram_locales file follows the format: > I have a few questions about the format. […] First of all, let me list my concerns: * Make the file as compact as possible * Make the parsing logic in coreboot as simple as possible * Make the read-only region compatible with some `string.h` functions --- For 1. I haven't find an easy logic to parse your structures, let me know if there's one I am not awared of. I have another idea: prepend one "type byte" in front of each strings. e.g. \x00 \x01 string_name_1 \x00 \x02 locale_id_1 \x00 \x03 localized_string_1 ... Hence our `search_for` will always point to the "type byte" and we could easily parse them by type enum ``` enum content_type { CONTENT_TYPE_STRING_NAME = 0x01, CONTENT_TYPE_LOCALE_ID = 0x02, CONTENT_TYPE_LOCALIZED = 0x03, }; ``` --- For 2. Adding version byte (maybe two bytes?) seems reasonable, I am not sure if we want a checksum -- If so, we might follow the similiar logic of ELOG? e.g. adding SIGNATURE, VERSION, CHEKCSUM File src/lib/ux_locales.c: https://review.coreboot.org/c/coreboot/+/75330/comment/615fe052_047a7046 : PS9, Line 101: const char *ux_locales_get_text(const char *name) > Add a unit test for this? I'll take a look at adding this. -- To view, visit https://review.coreboot.org/c/coreboot/+/75330?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e3c8d103c938a11b397c32c9228e44e31c3f01d Gerrit-Change-Number: 75330 Gerrit-PatchSet: 9 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 27 Jun 2023 10:17:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: acpi/acpi.c: Reduce boilerplate
by Arthur Heymans (Code Review) 27 Jun '23

27 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76127?usp=email ) Change subject: acpi/acpi.c: Reduce boilerplate ...................................................................... acpi/acpi.c: Reduce boilerplate Adding tables to R/XSDT, aligning current pointer, computing checksum is a lot of boilerplate that needs to be done for each table. TESTED on foxconn/g41. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: If4915b8cdfcfdbb34284ea75fa8a0fd23554152d --- M src/acpi/acpi.c 1 file changed, 126 insertions(+), 192 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/76127/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index cfc388b..5a571d7 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -27,6 +27,7 @@ #include <device/mmio.h> #include <device/pci.h> #include <pc80/mc146818rtc.h> +#include <stdint.h> #include <string.h> #include <types.h> #include <version.h> @@ -338,13 +339,11 @@ return current; } -static void acpi_create_madt(acpi_madt_t *madt) +static void acpi_create_madt(acpi_header_t *header, void *unused) { - acpi_header_t *header = &(madt->header); + acpi_madt_t *madt = (acpi_madt_t *)header; unsigned long current = (unsigned long)madt + sizeof(acpi_madt_t); - memset((void *)madt, 0, sizeof(acpi_madt_t)); - if (!header) return; @@ -371,10 +370,8 @@ if (CONFIG(ACPI_CUSTOM_MADT)) current = acpi_fill_madt(current); - /* (Re)calculate length and checksum. */ + /* (Re)calculate length . */ header->length = current - (unsigned long)madt; - - header->checksum = acpi_checksum((void *)madt, header->length); } static unsigned long acpi_fill_mcfg(unsigned long current) @@ -386,9 +383,9 @@ } /* MCFG is defined in the PCI Firmware Specification 3.0. */ -static void acpi_create_mcfg(acpi_mcfg_t *mcfg) +static void acpi_create_mcfg(acpi_header_t *header, void *unused) { - acpi_header_t *header = &(mcfg->header); + acpi_mcfg_t *mcfg = (acpi_mcfg_t *)header; unsigned long current = (unsigned long)mcfg + sizeof(acpi_mcfg_t); memset((void *)mcfg, 0, sizeof(acpi_mcfg_t)); @@ -409,9 +406,8 @@ if (CONFIG(ECAM_MMCONF_SUPPORT)) current = acpi_fill_mcfg(current); - /* (Re)calculate length and checksum. */ + /* (Re)calculate length */ header->length = current - (unsigned long)mcfg; - header->checksum = acpi_checksum((void *)mcfg, header->length); } static void *get_tcpa_log(u32 *size) @@ -439,14 +435,15 @@ return lasa; } -static void acpi_create_tcpa(acpi_tcpa_t *tcpa) +static void acpi_create_tcpa(acpi_header_t *header, void *unused) { - acpi_header_t *header = &(tcpa->header); + if (!CONFIG(TPM1)) + return; + + acpi_tcpa_t *tcpa = (acpi_tcpa_t *)header; u32 tcpa_log_len; void *lasa; - memset((void *)tcpa, 0, sizeof(acpi_tcpa_t)); - lasa = get_tcpa_log(&tcpa_log_len); if (!lasa) return; @@ -467,9 +464,6 @@ tcpa->platform_class = 0; tcpa->laml = tcpa_log_len; tcpa->lasa = (uintptr_t)lasa; - - /* Calculate checksum. */ - header->checksum = acpi_checksum((void *)tcpa, header->length); } static void *get_tpm2_log(u32 *size) @@ -497,14 +491,15 @@ return lasa; } -static void acpi_create_tpm2(acpi_tpm2_t *tpm2) +static void acpi_create_tpm2(acpi_header_t *header, void *unused) { - acpi_header_t *header = &(tpm2->header); + if (!CONFIG(TPM2)) + return; + + acpi_tpm2_t *tpm2 = (acpi_tpm2_t *)header; u32 tpm2_log_len; void *lasa; - memset((void *)tpm2, 0, sizeof(acpi_tpm2_t)); - /* * Some payloads like SeaBIOS depend on log area to use TPM2. * Get the memory size and address of TPM2 log area or initialize it. @@ -542,9 +537,6 @@ /* Fill the log area size and start address fields. */ tpm2->laml = tpm2_log_len; tpm2->lasa = (uintptr_t)lasa; - - /* Calculate checksum. */ - header->checksum = acpi_checksum((void *)tpm2, header->length); } static void acpi_ssdt_write_cbtable(void) @@ -570,7 +562,7 @@ acpigen_pop_len(); } -static void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) +static void acpi_create_ssdt_generator(acpi_header_t *ssdt, void *unused) { unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t); @@ -579,7 +571,7 @@ memcpy(&ssdt->signature, "SSDT", 4); ssdt->revision = get_acpi_table_revision(SSDT); memcpy(&ssdt->oem_id, OEM_ID, 6); - memcpy(&ssdt->oem_table_id, oem_table_id, 8); + memcpy(&ssdt->oem_table_id, ACPI_TABLE_CREATOR, 8); ssdt->oem_revision = 42; memcpy(&ssdt->asl_compiler_id, ASLC, 4); ssdt->asl_compiler_revision = asl_revision; @@ -1504,9 +1496,9 @@ return current; } -static void acpi_create_facs(acpi_facs_t *facs) +static void acpi_create_facs(void *header) { - memset((void *)facs, 0, sizeof(acpi_facs_t)); + acpi_facs_t *facs = header; memcpy(facs->signature, "FACS", 4); facs->length = sizeof(acpi_facs_t); @@ -1681,15 +1673,21 @@ } /* ACPI 3.0b */ -static void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length) +static void acpi_create_bert(acpi_header_t *header, void *unused) { - acpi_header_t *header = &(bert->header); + if (!CONFIG(ACPI_BERT)) + return; - memset(bert, 0, sizeof(acpi_bert_t)); + acpi_bert_t *bert = (acpi_bert_t *)header; if (!header) return; + void *region; + size_t size; + if (acpi_soc_get_bert_region(&region, &size) != CB_SUCCESS) + return; + memcpy(header->signature, "BERT", 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); @@ -1698,22 +1696,19 @@ header->length += sizeof(acpi_bert_t); header->revision = get_acpi_table_revision(BERT); - bert->error_region = region; - bert->region_length = length; - - /* Calculate checksums. */ - header->checksum = acpi_checksum((void *)bert, header->length); + bert->error_region = (uintptr_t)region; + bert->region_length = (size_t)size; } __weak void arch_fill_fadt(acpi_fadt_t *fadt) { } __weak void soc_fill_fadt(acpi_fadt_t *fadt) { } __weak void mainboard_fill_fadt(acpi_fadt_t *fadt) { } -static void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +static acpi_header_t *dsdt; +static void acpi_create_fadt(acpi_header_t *header, void *arg1) { - acpi_header_t *header = &(fadt->header); - - memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + acpi_fadt_t *fadt = (acpi_fadt_t *)header; + acpi_facs_t *facs = (acpi_facs_t *)(*(acpi_facs_t **)arg1); if (!header) return; @@ -1756,17 +1751,15 @@ soc_fill_fadt(fadt); mainboard_fill_fadt(fadt); - - header->checksum = - acpi_checksum((void *)fadt, header->length); } -static void acpi_create_lpit(acpi_lpit_t *lpit) +static void acpi_create_lpit(acpi_header_t *header, void *unused) { - acpi_header_t *header = &(lpit->header); - unsigned long current = (unsigned long)lpit + sizeof(acpi_lpit_t); + if (!CONFIG(ACPI_LPIT)) + return; - memset((void *)lpit, 0, sizeof(acpi_lpit_t)); + acpi_lpit_t *lpit = (acpi_lpit_t *)header; + unsigned long current = (unsigned long)lpit + sizeof(acpi_lpit_t); if (!header) return; @@ -1784,9 +1777,8 @@ current = acpi_fill_lpit(current); - /* (Re)calculate length and checksum. */ + /* (Re)calculate length. */ header->length = current - (unsigned long)lpit; - header->checksum = acpi_checksum((void *)lpit, header->length); } unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid) @@ -1815,6 +1807,57 @@ cbfs_preload(file); } +static void acpi_create_dsdt(acpi_header_t *header, void *dsdt_file_arg) +{ + dsdt = header; + acpi_header_t *dsdt_file = (acpi_header_t *)(*(acpi_header_t **)(dsdt_file_arg)); + unsigned long current = (unsigned long)header; + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, dsdt_file, sizeof(acpi_header_t)); + if (dsdt->length >= sizeof(acpi_header_t)) { + current += sizeof(acpi_header_t); + + acpigen_set_current((char *)current); + + if (CONFIG(ACPI_SOC_NVS)) + acpi_fill_gnvs(); + if (CONFIG(CHROMEOS_NVS)) + acpi_fill_cnvs(); + + for (const struct device *dev = all_devices; dev; dev = dev->next) + if (dev->ops && dev->ops->acpi_inject_dsdt) + dev->ops->acpi_inject_dsdt(dev); + current = (unsigned long)acpigen_get_current(); + memcpy((char *)current, + (char *)dsdt_file + sizeof(acpi_header_t), + dsdt->length - sizeof(acpi_header_t)); + current += dsdt->length - sizeof(acpi_header_t); + + /* (Re)calculate length. */ + dsdt->length = current - (unsigned long)dsdt; + } + + /* + * cbfs_unmap() uses mem_pool_free() which works correctly only + * if freeing is done in reverse order than memory allocation. + * This is why unmapping of dsdt_file must be done after + * unmapping slic file. + */ + cbfs_unmap(dsdt_file); +} + +static void acpi_create_slic(acpi_header_t *header, void *slic_file_arg) +{ + acpi_header_t *slic_file = (acpi_header_t *)(*(acpi_header_t **)slic_file_arg); + acpi_header_t *slic = header; + if (slic_file) { + memcpy(slic, slic_file, slic_file->length); + cbfs_unmap(slic_file); + } + +} + static uintptr_t coreboot_rsdp; uintptr_t get_coreboot_rsdp(void) @@ -1860,22 +1903,32 @@ acpi_rsdp_t *rsdp; acpi_rsdt_t *rsdt = NULL; acpi_xsdt_t *xsdt = NULL; - acpi_fadt_t *fadt = NULL; acpi_facs_t *facs = NULL; - acpi_header_t *slic_file, *slic = NULL; + acpi_header_t *slic_file; acpi_header_t *ssdt = NULL; - acpi_header_t *dsdt_file, *dsdt = NULL; - acpi_mcfg_t *mcfg = NULL; - acpi_tcpa_t *tcpa = NULL; - acpi_tpm2_t *tpm2 = NULL; - acpi_madt_t *madt = NULL; - acpi_lpit_t *lpit = NULL; - acpi_bert_t *bert = NULL; + acpi_header_t *dsdt_file; struct device *dev; unsigned long fw; size_t slic_size, dsdt_size; char oem_id[6], oem_table_id[8]; + const struct acpi_table_generator { + void (*create_table)(acpi_header_t *table, void *arg); + void *args; + size_t min_size; + } tables[] = { + { acpi_create_dsdt, &dsdt_file, sizeof(acpi_header_t) }, + { acpi_create_fadt, &facs, sizeof(acpi_fadt_t) }, + { acpi_create_slic, &slic_file, sizeof(acpi_header_t) }, + { acpi_create_ssdt_generator, NULL, sizeof(acpi_header_t) }, + { acpi_create_mcfg, NULL, sizeof(acpi_mcfg_t) }, + { acpi_create_tcpa, NULL, sizeof(acpi_tcpa_t) }, + { acpi_create_tpm2, NULL, sizeof(acpi_tpm2_t) }, + { acpi_create_lpit, NULL, sizeof(acpi_lpit_t) }, + { acpi_create_madt, NULL, sizeof(acpi_header_t) }, + { acpi_create_bert, NULL, sizeof(acpi_bert_t) }, + }; + current = start; /* Align ACPI tables to 16byte */ @@ -1921,7 +1974,7 @@ ssdt->length = current - (unsigned long)ssdt; ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + acpi_create_ssdt_generator(ssdt, NULL); acpi_add_table(rsdp, ssdt); @@ -1981,145 +2034,26 @@ acpi_write_rsdt(rsdt, oem_id, oem_table_id); acpi_write_xsdt(xsdt, oem_id, oem_table_id); - printk(BIOS_DEBUG, "ACPI: * FACS\n"); current = ALIGN_UP(current, 64); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); facs = (acpi_facs_t *)current; current += sizeof(acpi_facs_t); current = acpi_align_current(current); acpi_create_facs(facs); - printk(BIOS_DEBUG, "ACPI: * DSDT\n"); - dsdt = (acpi_header_t *)current; - memcpy(dsdt, dsdt_file, sizeof(acpi_header_t)); - if (dsdt->length >= sizeof(acpi_header_t)) { - current += sizeof(acpi_header_t); - - acpigen_set_current((char *)current); - - if (CONFIG(ACPI_SOC_NVS)) - acpi_fill_gnvs(); - if (CONFIG(CHROMEOS_NVS)) - acpi_fill_cnvs(); - - for (dev = all_devices; dev; dev = dev->next) - if (dev->ops && dev->ops->acpi_inject_dsdt) - dev->ops->acpi_inject_dsdt(dev); - current = (unsigned long)acpigen_get_current(); - memcpy((char *)current, - (char *)dsdt_file + sizeof(acpi_header_t), - dsdt->length - sizeof(acpi_header_t)); - current += dsdt->length - sizeof(acpi_header_t); - - /* (Re)calculate length and checksum. */ - dsdt->length = current - (unsigned long)dsdt; - dsdt->checksum = 0; - dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); - } - - current = acpi_align_current(current); - - printk(BIOS_DEBUG, "ACPI: * FADT\n"); - fadt = (acpi_fadt_t *)current; - current += sizeof(acpi_fadt_t); - current = acpi_align_current(current); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); - - if (slic_file) { - printk(BIOS_DEBUG, "ACPI: * SLIC\n"); - slic = (acpi_header_t *)current; - memcpy(slic, slic_file, slic_file->length); - current += slic_file->length; + for (size_t i = 0; i < ARRAY_SIZE(tables); i++) { + acpi_header_t *header = (acpi_header_t *)current; + memset(header, 0, tables[i].min_size); + tables[i].create_table(header, tables[i].args); + if (header->length < tables[i].min_size) + continue; + header->checksum = 0; + header->checksum = acpi_checksum((void *)header, header->length); + current += header->length; current = acpi_align_current(current); - acpi_add_table(rsdp, slic); - cbfs_unmap(slic_file); - } - - /* - * cbfs_unmap() uses mem_pool_free() which works correctly only - * if freeing is done in reverse order than memory allocation. - * This is why unmapping of dsdt_file must be done after - * unmapping slic file. - */ - cbfs_unmap(dsdt_file); - - printk(BIOS_DEBUG, "ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - if (ssdt->length > sizeof(acpi_header_t)) { - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - current = acpi_align_current(current); - } - - printk(BIOS_DEBUG, "ACPI: * MCFG\n"); - mcfg = (acpi_mcfg_t *)current; - acpi_create_mcfg(mcfg); - if (mcfg->header.length > sizeof(acpi_mcfg_t)) { - current += mcfg->header.length; - current = acpi_align_current(current); - acpi_add_table(rsdp, mcfg); - } - - if (CONFIG(TPM1)) { - printk(BIOS_DEBUG, "ACPI: * TCPA\n"); - tcpa = (acpi_tcpa_t *)current; - acpi_create_tcpa(tcpa); - if (tcpa->header.length >= sizeof(acpi_tcpa_t)) { - current += tcpa->header.length; - current = acpi_align_current(current); - acpi_add_table(rsdp, tcpa); - } - } - - if (CONFIG(TPM2)) { - printk(BIOS_DEBUG, "ACPI: * TPM2\n"); - tpm2 = (acpi_tpm2_t *)current; - acpi_create_tpm2(tpm2); - if (tpm2->header.length >= sizeof(acpi_tpm2_t)) { - current += tpm2->header.length; - current = acpi_align_current(current); - acpi_add_table(rsdp, tpm2); - } - } - - if (CONFIG(ACPI_LPIT)) { - printk(BIOS_DEBUG, "ACPI: * LPIT\n"); - - lpit = (acpi_lpit_t *)current; - acpi_create_lpit(lpit); - if (lpit->header.length >= sizeof(acpi_lpit_t)) { - current += lpit->header.length; - current = acpi_align_current(current); - acpi_add_table(rsdp, lpit); - } - } - - printk(BIOS_DEBUG, "ACPI: * MADT\n"); - - madt = (acpi_madt_t *)current; - acpi_create_madt(madt); - if (madt->header.length > sizeof(acpi_madt_t)) { - current += madt->header.length; - acpi_add_table(rsdp, madt); - } - - current = acpi_align_current(current); - - if (CONFIG(ACPI_BERT)) { - void *region; - size_t size; - bert = (acpi_bert_t *)current; - if (acpi_soc_get_bert_region(&region, &size) == CB_SUCCESS) { - printk(BIOS_DEBUG, "ACPI: * BERT\n"); - acpi_write_bert(bert, (uintptr_t)region, size); - if (bert->header.length >= sizeof(acpi_bert_t)) { - current += bert->header.length; - acpi_add_table(rsdp, bert); - } - current = acpi_align_current(current); - } + printk(BIOS_DEBUG, "ACPI: * %.4s\n", header->signature); + acpi_add_table(rsdp, header); } printk(BIOS_DEBUG, "current = %lx\n", current); -- To view, visit https://review.coreboot.org/c/coreboot/+/76127?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4915b8cdfcfdbb34284ea75fa8a0fd23554152d Gerrit-Change-Number: 76127 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/nissa: Setup driver for gothrax
by Paul Menzel (Code Review) 27 Jun '23

27 Jun '23

Attention is currently required from: Derek Huang, Henry Sun, Tarun Tuli, Yunlong Jia. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76104?usp=email ) Change subject: mb/google/nissa: Setup driver for gothrax ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/76104/comment/5ac05791_d9b5daa2 : PS1, Line 7: Setup The verb is spelled with a space: Set up. https://review.coreboot.org/c/coreboot/+/76104/comment/d463d329_2736c9fb : PS1, Line 9: Setup Ditto: The verb is spelled with a space: Set up. https://review.coreboot.org/c/coreboot/+/76104/comment/9bb4ca6f_d03c65b4 : PS1, Line 11: What source did you use for your changes? Schematics? File src/mainboard/google/brya/Kconfig.name: https://review.coreboot.org/c/coreboot/+/76104/comment/fdb66490_b4230782 : PS1, Line 389: select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER Why select this? -- To view, visit https://review.coreboot.org/c/coreboot/+/76104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1203ca13bd55b8ab96ce5d323a36ffde06860fa9 Gerrit-Change-Number: 76104 Gerrit-PatchSet: 1 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Comment-Date: Tue, 27 Jun 2023 09:39:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: acpi: Add SPCR table
by Lean Sheng Tan (Code Review) 27 Jun '23

27 Jun '23

Attention is currently required from: Arthur Heymans, Benjamin Doron, Lance Zhao, Nico Huber, Tim Wawrzynczak. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75685?usp=email ) Change subject: acpi: Add SPCR table ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64e624c17a27b9215a8ba83bd6cbb2c0a7aa1dfc Gerrit-Change-Number: 75685 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 27 Jun 2023 09:33:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/google/nissa/var/gothrax: Initialise overridetree
by Yunlong Jia (Code Review) 27 Jun '23

27 Jun '23

Attention is currently required from: Derek Huang, Felix Singer, Henry Sun, Tarun Tuli. Yunlong Jia has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76013?usp=email ) Change subject: mb/google/nissa/var/gothrax: Initialise overridetree ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/gothrax/overridetree.cb: https://review.coreboot.org/c/coreboot/+/76013/comment/ddc6c520_4ac574f9 : PS2, Line 35: register "ext_fivr_settings" = "{ : .configure_ext_fivr = 1, : .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, : .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, : .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, : .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, : .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, : .v1p05_voltage_mv = 1050, : .vnn_voltage_mv = 780, : .vnn_sx_voltage_mv = 1050, : .v1p05_icc_max_ma = 500, : .vnn_icc_max_ma = 500, : }" > missing tabs Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd9788a75f9c342f85d6e1a3d54327d64797dd8 Gerrit-Change-Number: 76013 Gerrit-PatchSet: 3 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Comment-Date: Tue, 27 Jun 2023 09:26:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/uldren: Modify DPTF parameters
by Dtrain Hsu (Code Review) 27 Jun '23

27 Jun '23

Attention is currently required from: Shou-Chieh Hsu, Sumeet R Pawnikar, Tarun Tuli. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76105?usp=email ) Change subject: mb/google/nissa/var/uldren: Modify DPTF parameters ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/uldren/overridetree.cb: https://review.coreboot.org/c/coreboot/+/76105/comment/f4a7468d_606f5bf8 : PS1, Line 180: 130 > Where can I find this SSDT sheet? In Project_Uldren_Thermal_paramters_list_2023_0626.xlsx. > What's the comment number in which I can find this SSDT sheet in bug? https://partnerissuetracker.corp.google.com/issues/282598257#comment16. -- To view, visit https://review.coreboot.org/c/coreboot/+/76105?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5bbb3aa3b036a1eae8a95f63b570db2dc6da978 Gerrit-Change-Number: 76105 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Paul Yang <paul.f.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Tue, 27 Jun 2023 09:17:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/google/nissa/var/gothrax: Initialise overridetree
by Derek Huang (Code Review) 27 Jun '23

27 Jun '23

Attention is currently required from: Felix Singer, Henry Sun, Tarun Tuli, Yunlong Jia. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76013?usp=email ) Change subject: mb/google/nissa/var/gothrax: Initialise overridetree ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/gothrax/overridetree.cb: https://review.coreboot.org/c/coreboot/+/76013/comment/0c903bc5_f711a0ff : PS2, Line 35: register "ext_fivr_settings" = "{ : .configure_ext_fivr = 1, : .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, : .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, : .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, : .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, : .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, : .v1p05_voltage_mv = 1050, : .vnn_voltage_mv = 780, : .vnn_sx_voltage_mv = 1050, : .v1p05_icc_max_ma = 500, : .vnn_icc_max_ma = 500, : }" missing tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/76013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd9788a75f9c342f85d6e1a3d54327d64797dd8 Gerrit-Change-Number: 76013 Gerrit-PatchSet: 2 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Comment-Date: Tue, 27 Jun 2023 09:15:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/uldren: Modify DPTF parameters
by Sumeet R Pawnikar (Code Review) 27 Jun '23

27 Jun '23

Attention is currently required from: Dtrain Hsu, Shou-Chieh Hsu, Tarun Tuli. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76105?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/nissa/var/uldren: Modify DPTF parameters ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/uldren/overridetree.cb: https://review.coreboot.org/c/coreboot/+/76105/comment/4b85ec50_41103e3d : PS1, Line 180: 130 > Thanks for review. Since the settings here will be filled in SSDT, you can refer to SSDT sheet. Where can I find this SSDT sheet? What's the comment number in which I can find this SSDT sheet in bug? -- To view, visit https://review.coreboot.org/c/coreboot/+/76105?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5bbb3aa3b036a1eae8a95f63b570db2dc6da978 Gerrit-Change-Number: 76105 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Paul Yang <paul.f.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Tue, 27 Jun 2023 09:09:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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