Wonkyu Kim has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/74410?usp=email )
Change subject: soc/intel/meteorlake: Print CPU frequency info in log
......................................................................
Abandoned
create new CL: https://review.coreboot.org/c/coreboot/+/76124
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76124?usp=email )
Change subject: soc/intel/meteorlake: Report CPU clock info
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76124/comment/a2087b1c_cbfd7506 :
PS3, Line 7: soc/intel/meteorlake: Report CPU clock info
please highlight the commit msg with the possible output w/ ur cl
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Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76125?usp=email )
Change subject: mb/google/dedede/var/taranza: Disable EXT_VR
......................................................................
mb/google/dedede/var/taranza: Disable EXT_VR
The taranza removed the APW8738BQBI and
"disable_external_bypass_vr" should be set to "1" to disable
BUG=b:288978340
TEST=emerge-dedede coreboot
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com>
Change-Id: I0a849fbfacba1d200c969c66bb058863d7ab3085
---
M src/mainboard/google/dedede/variants/taranza/overridetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/76125/1
diff --git a/src/mainboard/google/dedede/variants/taranza/overridetree.cb b/src/mainboard/google/dedede/variants/taranza/overridetree.cb
index e3df1f2..fa8d409 100644
--- a/src/mainboard/google/dedede/variants/taranza/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/taranza/overridetree.cb
@@ -53,6 +53,9 @@
register "DdiPortAHpd" = "1"
register "DdiPortADdc" = "1"
+ # Does not support external vnn power rail
+ register "disable_external_bypass_vr" = "1"
+
# USB Port Configuration
register "usb2_ports[0]" = "{
.enable = 1,
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ChiaLing has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75681?usp=email )
Change subject: mb/google/dedede/var/dibbi: Update power limits
......................................................................
Patch Set 11:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75681/comment/aa6f3000_708adedc :
PS10, Line 9: limit
> limit*s*?
Done
https://review.coreboot.org/c/coreboot/+/75681/comment/a4e9df7c_4bb620fa :
PS10, Line 10:
> What were the default(?) limits before your change?
Before my change, power limits are set in devicetree.
File src/mainboard/google/dedede/variants/dibbi/ramstage.c:
https://review.coreboot.org/c/coreboot/+/75681/comment/76dc51bf_f6785522 :
PS10, Line 6: .
> Not needed.
Done
https://review.coreboot.org/c/coreboot/+/75681/comment/8047eb4a_f57a529d :
PS10, Line 14: b/w
> I’d write between, as there are non-native readers too.
Done
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Hello Reka Norman, Ryan Lin, Sumeet R Pawnikar, Zhuohao Lee, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75681?usp=email
to look at the new patch set (#11).
The following approvals got outdated and were removed:
Code-Review+2 by Reka Norman, Code-Review+2 by Sumeet R Pawnikar, Verified+1 by build bot (Jenkins)
Change subject: mb/google/dedede/var/dibbi: Update power limits
......................................................................
mb/google/dedede/var/dibbi: Update power limits
Add ramstage.c in Makefile.inc and update Dibbi power limits in dibbi ramstage.c.
BUG=b:281479111
TEST=emerge-dedede coreboot and check psys and PLx value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com>
Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6
---
M src/mainboard/google/dedede/variants/dibbi/Makefile.inc
A src/mainboard/google/dedede/variants/dibbi/ramstage.c
2 files changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/75681/11
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