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Hello Eric Lai, Ivy Jian, Kapil Porwal, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
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Change subject: soc/intel/meteorlake: Introduce different SoC flavors of Meteor Lake
......................................................................
soc/intel/meteorlake: Introduce different SoC flavors of Meteor Lake
This patch introduces the different SoC flavors of Intel Meteor Lake as:
* MTL-U
* MTL-P
* MTL-S
MTL-U and MTL-P are PCH less designs, while MTL-S is with PCH die.
The task for mainboard is to specify the correct SoC type rather than
selecting the MTL SoC by default.
This change is necessary to support the different SoC flavors of Intel
Meteor Lake.
BUG=b:276697173
TEST=Able to build and boot google/rex.
Change-Id: I27404bbbd0b489412953118e140f6f39b6e43426
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/meteorlake/Kconfig
1 file changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/75606/2
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Subrata Banik has uploaded a new patch set (#5) to the change originally created by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/75529?usp=email )
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Change subject: soc/intel/meteorlake: Hook up UPD PchHdaSdiEnable
......................................................................
soc/intel/meteorlake: Hook up UPD PchHdaSdiEnable
Hook the PchHdaSdiEnable UPD so that mainboard can change the
settings via devicetree. PchHdaSdiEnable UPD enable HDA SDI lanes.
BUG=b:273962021
TEST=Verified the settings on google/rex using debug FSP logs.
Change-Id: I43f1e59d28fc07218f8e25266f8ce3bdcf3f6e5c
Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com>
---
M src/soc/intel/meteorlake/chip.h
M src/soc/intel/meteorlake/romstage/fsp_params.c
2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/75529/5
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Change subject: soc/intel/meteorlake: Introduce different SoC flavors of Meteor Lake
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75606/comment/f6ca646e_679f5eb2 :
PS1, Line 10: for example: MTL-U, MTL-P and MTL-S.
> Could you list all?
Acknowledged
https://review.coreboot.org/c/coreboot/+/75606/comment/30a61929_e9d19501 :
PS1, Line 13: ask
> task
Acknowledged
File src/soc/intel/meteorlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/75606/comment/9bc38a61_46e6ea79 :
PS1, Line 20: Important to note that MTL-S SoC combines Compute, GFX, SoC, IOE and PCH die.
> Maybe: […]
Acknowledged
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Change subject: allocator_v4: Treat above 4G resources more natively
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75012/comment/43fba777_b8cb9261 :
PS4, Line 45: Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/65413
> I was a little confused, thinking this commit replaces the one mentioned above. […]
We reverted the original.
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Change subject: soc/amd/picasso/chip: use common data fabric domain resource code
......................................................................
Patch Set 12: Code-Review+1
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Change subject: mb/google/myst: Add USB config
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75574/comment/07f43f48_f4f4fa55 :
PS2, Line 9: FSP
In two years, nobody will remember and having to dig through Gerrit comments is going to be very time-consuming. I think,
> … since early-bringup FSP …
would be helpful.
https://review.coreboot.org/c/coreboot/+/75574/comment/5b106c93_88896838 :
PS2, Line 14: verify USB works
> We're still in early bringup. This enables testing. […]
Maybe you can be more specific: verify hubs and attached USB devices are listed in `lsusb`
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Change subject: soc/amd/common/data_fabric/domain: write _STA method in SSDT
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
This seems odd, I wonder why it should have an _STA object at all?
Without _STA, OSPM is supposed to assume the device is there and
working and what other state could we expected for a domain?
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Change subject: allocator_v4: Treat above 4G resources more natively
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75012/comment/892b3cb0_5d5907e8 :
PS4, Line 45: Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/65413
I was a little confused, thinking this commit replaces the one mentioned above. But the mentioned shange-set is denoted as merged.
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Change subject: soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt
......................................................................
Patch Set 11:
(3 comments)
File src/soc/amd/common/block/data_fabric/domain.c:
https://review.coreboot.org/c/coreboot/+/74843/comment/86ba81d1_09f87009 :
PS11, Line 169: if (base > PCI_IO_CONFIG_LAST_PORT || limit < PCI_IO_CONFIG_INDEX) {
> I wonder what ACPI says about having a resource producer that covers this […]
i can try that. Arthur's code didn't handle this as a special case, but all reference code i looked at had this handled separately
https://review.coreboot.org/c/coreboot/+/74843/comment/a9306646_7bd1940f :
PS11, Line 176: /*spit IO range to not cover PCI config IO ports*/
> Whitspace around comment marks and *split*.
just fixed that in my local tree; will mark this as resolved once i've pushed the new version
https://review.coreboot.org/c/coreboot/+/74843/comment/bc6a8864_f4e22e94 :
PS11, Line 168:
: if (base > PCI_IO_CONFIG_LAST_PORT || limit < PCI_IO_CONFIG_INDEX) {
: /* no overlap with PCI config IO ports */
: write_ssdt_domain_io_range_helper(base, limit);
: } else {/* overlap with PCI config IO ports */
: if (base == PCI_IO_CONFIG_INDEX && limit == PCI_IO_CONFIG_LAST_PORT)
: return; /* IO range exactly covers the PCI config IO ports */
: if (base < PCI_IO_CONFIG_INDEX && limit > PCI_IO_CONFIG_LAST_PORT) {
: /*spit IO range to not cover PCI config IO ports*/
: write_ssdt_domain_io_range_helper(base, PCI_IO_CONFIG_INDEX - 1);
: write_ssdt_domain_io_range_helper(PCI_IO_CONFIG_LAST_PORT + 1, limit);
: } else if (limit <= PCI_IO_CONFIG_LAST_PORT) {
: write_ssdt_domain_io_range_helper(base, PCI_IO_CONFIG_INDEX - 1);
: } else { /* base >= PCI_IO_CONFIG_INDEX */
: write_ssdt_domain_io_range_helper(PCI_IO_CONFIG_LAST_PORT + 1, limit);
: }
: }
> Much simpler and should work too AFAICT: […]
will look into this to make sure that it covers all cases correctly, but from a quick look it looks good to me
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