coreboot-gerrit June 2023

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Add RMT config
by Felix Singer (Code Review) 02 Jun '23

02 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Naresh Solanki, Tim Chu. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75416?usp=email ) Change subject: soc/intel/xeon_sp/spr: Add RMT config ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/xeon_sp/spr/romstage.c: https://review.coreboot.org/c/coreboot/+/75416/comment/0f54173e_dad33a91 : PS3, Line 221: /* Enable RMT based on build config, default is disabled */ The comment seems superfluous. CONFIG() mostly refers to Kconfig variables. Also, please don't document the default value in code comments (even if in this case the default value will probably never change), otherwise it's too much maintenance. So please remove it. -- To view, visit https://review.coreboot.org/c/coreboot/+/75416?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b9276116c22cfbbec132d7a1b0026a52a51398a Gerrit-Change-Number: 75416 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 02 Jun 2023 20:23:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: amdfwtool: Only use AMD_FW_RECOVERYAB_A on phoenix
by Martin L Roth (Code Review) 02 Jun '23

02 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74971?usp=email ) Change subject: amdfwtool: Only use AMD_FW_RECOVERYAB_A on phoenix ...................................................................... amdfwtool: Only use AMD_FW_RECOVERYAB_A on phoenix BUG=285390041 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I4321c6a8553b470096aec263fb4b15b831efae7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74971 Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/amdfwtool/amdfwtool.c 1 file changed, 5 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Jon Murphy: Looks good to me, approved Tim Van Patten: Looks good to me, approved diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 275e49d..1b2b005 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -982,6 +982,7 @@ uint32_t current_table_save; bool recovery_ab = cb_config->recovery_ab; ish_directory_table *ish_a_dir = NULL, *ish_b_dir = NULL; + bool use_only_a = (cb_config->soc_id == PLATFORM_PHOENIX); /* TODO: b:285390041 */ /* This function can create a primary table, a secondary table, or a * flattened table which contains all applicable types. These if-else @@ -1116,10 +1117,12 @@ AMD_FW_RECOVERYAB_A, cb_config->soc_id); if (pspdir2_b != NULL) integrate_psp_ab(ctx, pspdir, pspdir2_b, ish_b_dir, - AMD_FW_RECOVERYAB_B, cb_config->soc_id); + use_only_a ? AMD_FW_RECOVERYAB_A : AMD_FW_RECOVERYAB_B, + cb_config->soc_id); else integrate_psp_ab(ctx, pspdir, pspdir2, ish_a_dir, - AMD_FW_RECOVERYAB_B, cb_config->soc_id); + use_only_a ? AMD_FW_RECOVERYAB_A : AMD_FW_RECOVERYAB_B, + cb_config->soc_id); count = pspdir->header.num_entries; } else if (pspdir2 != NULL) { -- To view, visit https://review.coreboot.org/c/coreboot/+/74971?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4321c6a8553b470096aec263fb4b15b831efae7f Gerrit-Change-Number: 74971 Gerrit-PatchSet: 7 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/phoenix/Kconfig: Prevent changes to AMD_FWM_POSITION_INDEX
by Martin L Roth (Code Review) 02 Jun '23

02 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74249?usp=email ) Change subject: soc/amd/phoenix/Kconfig: Prevent changes to AMD_FWM_POSITION_INDEX ...................................................................... soc/amd/phoenix/Kconfig: Prevent changes to AMD_FWM_POSITION_INDEX The phoenix SoC does not support multiple EFS locations. Set the default to the only valid value and prevent mainboard overrides by making the option non-user-configurable. TEST=build birman-phoenix Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I0f720dbadf2d28a3c39daa4bd653a407be4893d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74249 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/soc/amd/phoenix/Kconfig 1 file changed, 2 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index adb990b..933043b 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -316,24 +316,8 @@ menu "PSP Configuration Options" config AMD_FWM_POSITION_INDEX - int "Firmware Directory Table location (0 to 5)" - range 0 5 - default 0 if BOARD_ROMSIZE_KB_512 - default 1 if BOARD_ROMSIZE_KB_1024 - default 2 if BOARD_ROMSIZE_KB_2048 - default 3 if BOARD_ROMSIZE_KB_4096 - default 4 if BOARD_ROMSIZE_KB_8192 - default 5 if BOARD_ROMSIZE_KB_16384 - help - Typically this is calculated by the ROM size, but there may - be situations where you want to put the firmware directory - table in a different location. - 0: 512 KB - 0xFFFA0000 - 1: 1 MB - 0xFFF20000 - 2: 2 MB - 0xFFE20000 - 3: 4 MB - 0xFFC20000 - 4: 8 MB - 0xFF820000 - 5: 16 MB - 0xFF020000 + int + default 5 comment "AMD Firmware Directory Table set to location for 512KB ROM" depends on AMD_FWM_POSITION_INDEX = 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/74249?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f720dbadf2d28a3c39daa4bd653a407be4893d0 Gerrit-Change-Number: 74249 Gerrit-PatchSet: 9 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/phoenix/Kconfig: Prevent changes to AMD_FWM_POSITION_INDEX
by Martin L Roth (Code Review) 02 Jun '23

02 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Paul Menzel. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74249?usp=email ) Change subject: soc/amd/phoenix/Kconfig: Prevent changes to AMD_FWM_POSITION_INDEX ...................................................................... Patch Set 8: (1 comment) File src/soc/amd/phoenix/Kconfig: https://review.coreboot.org/c/coreboot/+/74249/comment/0fdae952_7594093c : PS8, Line 320: default 5 > There may be a very slim chance to fit in 8m, but I'd think 16m is the realistic minimum for phoenix […] Yes. I believe that 16MiB flash or larger is a requirement for Phoenix & newer SOCs. -- To view, visit https://review.coreboot.org/c/coreboot/+/74249?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f720dbadf2d28a3c39daa4bd653a407be4893d0 Gerrit-Change-Number: 74249 Gerrit-PatchSet: 8 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Jun 2023 20:13:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/qemu: Revise q35 configs
by Felix Singer (Code Review) 02 Jun '23

02 Jun '23

Attention is currently required from: Arthur Heymans, Nico Huber. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67026?usp=email ) Change subject: util/qemu: Revise q35 configs ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67026?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23746b642329356c6767b04ec177cd9411e3adb9 Gerrit-Change-Number: 67026 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 02 Jun 2023 20:07:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt
by Felix Held (Code Review) 02 Jun '23

02 Jun '23

Attention is currently required from: Arthur Heymans, Fred Reitberger, Jason Glenesk, Matt DeVillier, Nico Huber, Raul Rangel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74843?usp=email ) Change subject: soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt ...................................................................... Patch Set 11: (1 comment) File src/soc/amd/common/block/data_fabric/domain.c: https://review.coreboot.org/c/coreboot/+/74843/comment/92ccf558_200e1aec : PS11, Line 169: if (base > PCI_IO_CONFIG_LAST_PORT || limit < PCI_IO_CONFIG_INDEX) { > i can try that. […] figured out why this is done: when not splitting this, the 16 bit length field of the acpi resource gets truncated in the case of this covering all io ports and linux will heavily complain about not having usable io space. that also explains why the multi pci root domain code where the io space is split between the pci root domains just worked without having this special case -- To view, visit https://review.coreboot.org/c/coreboot/+/74843?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf6d38a8ef5bb0163c4d1c021bf892c323d9a448 Gerrit-Change-Number: 74843 Gerrit-PatchSet: 11 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Jun 2023 18:36:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: lib/dimm_info_util.c: Add newlines to log messages
by Felix Singer (Code Review) 02 Jun '23

02 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Martin L Roth. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75589?usp=email ) Change subject: lib/dimm_info_util.c: Add newlines to log messages ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75589?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f61c80385f384a3734a5122ccb4161c1ed7c6c5 Gerrit-Change-Number: 75589 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Jun 2023 18:05:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for SataPortsEnable
by Felix Singer (Code Review) 02 Jun '23

02 Jun '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75553?usp=email ) Change subject: soc/intel/apollolake: Switch to snake case for SataPortsEnable ...................................................................... soc/intel/apollolake: Switch to snake case for SataPortsEnable For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsEnable'. Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553 Reviewed-by: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jan Samek <jan.samek(a)siemens.com> --- M src/mainboard/intel/apollolake_rvp/devicetree.cb M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/leafhill/devicetree.cb M src/mainboard/intel/minnow3/devicetree.cb M src/mainboard/kontron/mal10/variants/mal10/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb M src/mainboard/starlabs/lite/variants/glk/devicetree.cb M src/mainboard/starlabs/lite/variants/glkr/devicetree.cb M src/mainboard/up/squared/devicetree.cb M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 16 files changed, 28 insertions(+), 28 deletions(-) Approvals: Felix Singer: Looks good to me, approved Himanshu Sahdev: Looks good to me, but someone else must approve build bot (Jenkins): Verified Jan Samek: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb index a983807..bf20913 100644 --- a/src/mainboard/intel/apollolake_rvp/devicetree.cb +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -21,8 +21,8 @@ device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" end device pci 13.0 on end # - PCIe-A 0 device pci 13.2 on end # - Onboard Lan diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 551fc60..294d468 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -121,8 +121,8 @@ device pci 0f.2 on end # - Heci3 device pci 11.0 off end # - ISH device pci 12.0 on # - SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" end device pci 13.0 off end # - PCIe-A 0 Slot 1 device pci 13.1 off end # - PCIe-A 1 diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb index 0a152b6..c1bfb97 100644 --- a/src/mainboard/intel/leafhill/devicetree.cb +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -21,8 +21,8 @@ device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" end device pci 13.0 on end # - PCIe-A 0 device pci 13.2 on end # - Onboard Lan diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb index 0a152b6..c1bfb97 100644 --- a/src/mainboard/intel/minnow3/devicetree.cb +++ b/src/mainboard/intel/minnow3/devicetree.cb @@ -21,8 +21,8 @@ device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" end device pci 13.0 on end # - PCIe-A 0 device pci 13.2 on end # - Onboard Lan diff --git a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb index a2a9df4..734f3f3 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb +++ b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb @@ -19,8 +19,8 @@ device pci 0f.0 on end # TXE device pci 11.0 off end # ISH device pci 12.0 on # SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" end device pci 13.0 on # PCIe-A 1 (Root Port 2) register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index a08f053..5d4acd8 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -69,8 +69,8 @@ device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" register "DisableSataSalpSupport" = "1" end device pci 13.0 on # - RP 2 - PCIe A 0 - MACPHY diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index 1291497..7054413 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -67,8 +67,8 @@ device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" register "sata_ports_ssd[0]" = "1" register "sata_ports_ssd[1]" = "1" register "DisableSataSalpSupport" = "1" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index 56d93aa..472f5ba 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -64,8 +64,8 @@ device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" register "DisableSataSalpSupport" = "1" end device pci 13.0 on # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 1c5f797..baaff1e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -58,8 +58,8 @@ device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" register "DisableSataSalpSupport" = "1" end device pci 13.0 on # - RP 2 - PCIe A 0 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index b308ab2..52fcd49 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -67,8 +67,8 @@ device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" register "sata_ports_ssd[0]" = "1" register "sata_ports_ssd[1]" = "1" register "DisableSataSalpSupport" = "1" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index 1885e81..dc66be6 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -38,8 +38,8 @@ device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH device pci 12.0 on # - SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" register "sata_ports_ssd[0]" = "1" register "sata_ports_ssd[1]" = "1" register "DisableSataSalpSupport" = "1" diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb index f1ace5a..fb9070f 100644 --- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb @@ -71,7 +71,7 @@ device ref heci2 on end device ref heci3 on end device ref sata on - register "SataPortsEnable[0]" = "1" + register "sata_ports_enable[0]" = "1" end device ref xhci on # Motherboard USB Type C diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index 71932a6..b4e627c 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -71,7 +71,7 @@ device ref heci2 on end device ref heci3 on end device ref sata on - register "SataPortsEnable[0]" = "1" + register "sata_ports_enable[0]" = "1" end device ref xhci on # Motherboard USB Type C diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index 4b0d5f7..4f5a91c 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -35,8 +35,8 @@ device pci 0f.0 on end # - TXE device pci 11.0 off end # - ISH device pci 12.0 on # - SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" end device pci 13.0 on end # - PCIe-A 1 - PcieRootPort[2] device pci 13.1 on end # - PCIe-A 2 - PcieRootPort[3] diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 7147011..04aa2eb 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -737,7 +737,7 @@ if (is_devfn_enabled(PCH_DEVFN_SATA)) { silconfig->SataSalpSupport = !(cfg->DisableSataSalpSupport); silconfig->SpeedLimit = cfg->sata_speed; - memcpy(silconfig->SataPortsEnable, cfg->SataPortsEnable, + memcpy(silconfig->SataPortsEnable, cfg->sata_ports_enable, sizeof(silconfig->SataPortsEnable)); memcpy(silconfig->SataPortsSolidStateDrive, cfg->sata_ports_ssd, sizeof(silconfig->SataPortsSolidStateDrive)); diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 45b60d3..b956252 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -107,7 +107,7 @@ uint8_t SataPortsHotPlug[2]; /* Sata Ports Enable */ - uint8_t SataPortsEnable[2]; + uint8_t sata_ports_enable[2]; /* Sata Ports Solid State Drive */ uint8_t sata_ports_ssd[2]; -- To view, visit https://review.coreboot.org/c/coreboot/+/75553?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Gerrit-Change-Number: 75553 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/amd/common/data_fabric/domain: write _STA method in SSDT
by Felix Held (Code Review) 02 Jun '23

02 Jun '23

Felix Held has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/74993?usp=email ) Change subject: soc/amd/common/data_fabric/domain: write _STA method in SSDT ...................................................................... Abandoned not needed -- To view, visit https://review.coreboot.org/c/coreboot/+/74993?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied48b48113f6e871e90d17cbd216be003f05b5ef Gerrit-Change-Number: 74993 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: abandon

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[XS] Change in coreboot[master]: mb/google/brya/var/kuldax: use RPL FSP headers
by Bob Moragues (Code Review) 02 Jun '23

02 Jun '23

Attention is currently required from: Bob Moragues, David Wu, Lucas Chen, Nick Vaccaro, Nick Vaccaro, Ren Kuo, Tarun Tuli. Bob Moragues has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75599?usp=email ) Change subject: mb/google/brya/var/kuldax: use RPL FSP headers ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbf8b26bc2bfee2559cce236bde80a99f8bff859 Gerrit-Change-Number: 75599 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Bob Moragues <moragues(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Jun 2023 17:43:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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