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Change subject: soc/amd/common/data_fabric/domain: write _STA method in SSDT
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
> the domain could be set to off in the devicetree. […]
SSDT wouldn't get generated for an `off` device (non of the device ops
would be called). I guess the original _STA method is just redundant.
Specs says
```
If a device object describes a device that is not on an enumerable
bus and the device object does not have an _STA object, then OSPM
assumes that the device is present, enabled, shown in the UI, and
functioning.
```
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Change subject: soc/amd/common/data_fabric/domain: write _STA method in SSDT
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
> This seems odd, I wonder why it should have an _STA object at all? […]
the domain could be set to off in the devicetree. not that that case would make much sense to me, but that would cover that case.
the newer socs from cezanne on had an _sta method that always returned 0xf which is why i implemented this
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Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75589?usp=email )
Change subject: lib/dimm_info_util.c: Add newlines to log messages
......................................................................
lib/dimm_info_util.c: Add newlines to log messages
Add newlines to log messages to prevent them from running into each
other.
Change-Id: I4f61c80385f384a3734a5122ccb4161c1ed7c6c5
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
---
M src/lib/dimm_info_util.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/75589/1
diff --git a/src/lib/dimm_info_util.c b/src/lib/dimm_info_util.c
index 3507366..d16cb46 100644
--- a/src/lib/dimm_info_util.c
+++ b/src/lib/dimm_info_util.c
@@ -26,7 +26,7 @@
out = MEMORY_BUS_WIDTH_8;
break;
default:
- printk(BIOS_NOTICE, "Unknown memory size %hu", data_width);
+ printk(BIOS_NOTICE, "Unknown memory size %hu\n", data_width);
/*
* The SMBIOS spec says we should set 0xFFFF on an unknown
* value, but we don't have a way of passing that signal via SPD
@@ -49,7 +49,7 @@
/* No extension bits */
break;
default:
- printk(BIOS_NOTICE, "Unknown number of extension bits %hu",
+ printk(BIOS_NOTICE, "Unknown number of extension bits %hu\n",
extension_bits);
break;
}
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Change subject: soc/intel/apollolake: Switch to snake case for SataPortsEnable
......................................................................
Patch Set 4: Code-Review+2
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Change subject: mb/google/rex: Create ovis variant
......................................................................
Patch Set 7: Code-Review+2
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Hello Eric Lai, Ivy Jian, Kapil Porwal, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75607?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Code-Review+2 by Eric Lai, Verified+1 by build bot (Jenkins)
The change is no longer submittable: Code-Review and Verified are unsatisfied now.
Change subject: mb/intel/mtlrvp: Select SOC_INTEL_METEORLAKE_U_P
......................................................................
mb/intel/mtlrvp: Select SOC_INTEL_METEORLAKE_U_P
Intel/MTLRVP is built with Intel Meteor Lake-U SoC, so select it.
Currently, there is no functional difference, but in the future FSP
UPD parameters can be overridden properly.
BUG=b:276697173
TEST=Able to build and boot intel/mtlrvp.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I8b1dec47ef9d12ac50317b86c4f0bc5fbe4e4dc3
---
M src/mainboard/intel/mtlrvp/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/75607/2
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Change subject: mb/{google,intel}: Choose correct SoC type between MTL-U/P and MTL-S
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75607/comment/f3be2792_3e6bcb0f :
PS1, Line 7: mb/{google,intel}: Choose correct SoC type between MTL-U/P and MTL-S
> I’d make it two commits: […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/75607/comment/0ec79c7d_b1ffddf1 :
PS1, Line 9: This patch ensures that mainboards built with Intel Meteor Lake SoC
: are able to specify the correct SoC type between MTL-U/P and MTL-S.
:
: It will help to override the FSP UPD parameters properly.
> Looking at the diff, that’s too broad? Maybe (for each board): […]
Acknowledged
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Change subject: allocator_v4: Treat above 4G resources more natively
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75012/comment/ac1e1299_0b1b0f3c :
PS4, Line 45: Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/65413
Sorry, the Gerrit search failed me.
Maybe clarify that with a small note:
> An earlier version is commit 117e43611548 (allocator_v4: Treat above 4G resources more natively), reverted by commit 38aafa329f45 due to missing top-down allocation.
Either way, feel free to mark my comment as resolved.
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Change subject: mb/google/rex: Create ovis variant
......................................................................
Patch Set 7:
(3 comments)
File src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/ec.h:
https://review.coreboot.org/c/coreboot/+/75385/comment/3bdcbc9e_b9fb772c :
PS4, Line 66: #define EC_ENABLE_MKBP_DEVICE
> Good question. Looking at brask, these are still enabled, so you are right.
Done
File src/mainboard/google/rex/variants/baseboard/ovis/memory.c:
https://review.coreboot.org/c/coreboot/+/75385/comment/991d7c04_a2f4a9c9 :
PS4, Line 16: .lpx_dq_map = {
> These values are the same as on Rex. Let me double check whether these needs to be adjusted.
I checked it with Intel-provided tools and also with schematics. It's the same as on Rex.
File src/mainboard/google/rex/variants/baseboard/ovis/memory.c:
https://review.coreboot.org/c/coreboot/+/75385/comment/348f6457_340d2259 :
PS5, Line 64: 0x66
> please reconfirm this value?
I checked it and it's the same as in case of Rex, so the value is correct.
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