coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

1 participants
5387 discussions

[S] Change in coreboot[master]: Docs: Update sphinx targets with the build directory
by Felix Singer (Code Review) 03 Jun '23

03 Jun '23

Attention is currently required from: Martin L Roth. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75499?usp=email ) Change subject: Docs: Update sphinx targets with the build directory ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75499?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab111e8feea8ec02260f39636e7c17fd1cae7c30 Gerrit-Change-Number: 75499 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Sat, 03 Jun 2023 20:47:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: Docs: Add a test target for the documentation
by Felix Singer (Code Review) 03 Jun '23

03 Jun '23

Attention is currently required from: Elyes Haouas, Martin L Roth. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75497?usp=email ) Change subject: Docs: Add a test target for the documentation ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75497?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5810643ee143f9db4f1cd388531161d4398d596c Gerrit-Change-Number: 75497 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 03 Jun 2023 20:47:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/common/crashlog: Add support for IOE die
by Martin L Roth (Code Review) 03 Jun '23

03 Jun '23

Attention is currently required from: Paul Menzel, Pratikkumar V Prajapati. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75475?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/common/crashlog: Add support for IOE die ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/include/intelblocks/crashlog.h: https://review.coreboot.org/c/coreboot/+/75475/comment/f3043d16_48c5c6db : PS4, Line 35: :16 Why is this a bitfield? -- To view, visit https://review.coreboot.org/c/coreboot/+/75475?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id90cf0095258c4f7003e4c5f2564bb763e687b75 Gerrit-Change-Number: 75475 Gerrit-PatchSet: 4 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Sat, 03 Jun 2023 20:43:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/common/crashlog: Add support for IOE die
by Martin L Roth (Code Review) 03 Jun '23

03 Jun '23

Attention is currently required from: Paul Menzel, Pratikkumar V Prajapati. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75475?usp=email ) Change subject: soc/intel/common/crashlog: Add support for IOE die ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75475/comment/f02dafce_29ec787d : PS4, Line 7: IOE die What is IOE? -- To view, visit https://review.coreboot.org/c/coreboot/+/75475?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id90cf0095258c4f7003e4c5f2564bb763e687b75 Gerrit-Change-Number: 75475 Gerrit-PatchSet: 4 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Sat, 03 Jun 2023 20:40:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/rex: Create karis variant
by Martin L Roth (Code Review) 03 Jun '23

03 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75551?usp=email ) Change subject: mb/google/rex: Create karis variant ...................................................................... mb/google/rex: Create karis variant Create the karis variant of the rex0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:285195072 TEST=util/abuild/abuild -p none -t google/rex -x -a make sure the build includes GOOGLE_KARIS Change-Id: I16d8b43390401789b87a6233238e37f32a17b46b Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75551 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/Kconfig.name A src/mainboard/google/rex/variants/karis/Makefile.inc A src/mainboard/google/rex/variants/karis/gpio.c A src/mainboard/google/rex/variants/karis/include/variant/ec.h A src/mainboard/google/rex/variants/karis/include/variant/gpio.h A src/mainboard/google/rex/variants/karis/memory/Makefile.inc A src/mainboard/google/rex/variants/karis/memory/dram_id.generated.txt A src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt A src/mainboard/google/rex/variants/karis/overridetree.cb 10 files changed, 80 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index e6313bf..89a2f81 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -83,11 +83,13 @@ config MAINBOARD_PART_NUMBER default "Rex" if BOARD_GOOGLE_REX0 || BOARD_GOOGLE_REX_EC_ISH default "Screebo" if BOARD_GOOGLE_SCREEBO + default "Karis" if BOARD_GOOGLE_KARIS config VARIANT_DIR string default "rex0" if BOARD_GOOGLE_REX0 || BOARD_GOOGLE_REX_EC_ISH default "screebo" if BOARD_GOOGLE_SCREEBO + default "karis" if BOARD_GOOGLE_KARIS config DIMM_SPD_SIZE default 512 diff --git a/src/mainboard/google/rex/Kconfig.name b/src/mainboard/google/rex/Kconfig.name index 9d81dc0..31b4cc6 100644 --- a/src/mainboard/google/rex/Kconfig.name +++ b/src/mainboard/google/rex/Kconfig.name @@ -13,6 +13,10 @@ bool "-> Screebo" select BOARD_GOOGLE_BASEBOARD_REX +config BOARD_GOOGLE_KARIS + bool "-> Karis" + select BOARD_GOOGLE_BASEBOARD_REX + config BOARD_GOOGLE_REX_EC_ISH bool "-> Rex EC ISH" select BOARD_GOOGLE_BASEBOARD_REX diff --git a/src/mainboard/google/rex/variants/karis/Makefile.inc b/src/mainboard/google/rex/variants/karis/Makefile.inc new file mode 100644 index 0000000..6c29346 --- /dev/null +++ b/src/mainboard/google/rex/variants/karis/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/rex/variants/karis/gpio.c b/src/mainboard/google/rex/variants/karis/gpio.c new file mode 100644 index 0000000..b6e346f --- /dev/null +++ b/src/mainboard/google/rex/variants/karis/gpio.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <types.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +static const struct cros_gpio cros_gpios[] = { +}; + +DECLARE_CROS_GPIOS(cros_gpios); + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/rex/variants/karis/include/variant/ec.h b/src/mainboard/google/rex/variants/karis/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/rex/variants/karis/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/rex/variants/karis/include/variant/gpio.h b/src/mainboard/google/rex/variants/karis/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/rex/variants/karis/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/rex/variants/karis/memory/Makefile.inc b/src/mainboard/google/rex/variants/karis/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/rex/variants/karis/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/rex/variants/karis/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/karis/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/rex/variants/karis/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/rex/variants/karis/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb new file mode 100644 index 0000000..6c284b3 --- /dev/null +++ b/src/mainboard/google/rex/variants/karis/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/meteorlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/75551?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16d8b43390401789b87a6233238e37f32a17b46b Gerrit-Change-Number: 75551 Gerrit-PatchSet: 5 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[master]: mb/google/brya/var/anahera: Generate RAM ID for K4UCE3Q4AB-MGCL
by Martin L Roth (Code Review) 03 Jun '23

03 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75156?usp=email ) Change subject: mb/google/brya/var/anahera: Generate RAM ID for K4UCE3Q4AB-MGCL ...................................................................... mb/google/brya/var/anahera: Generate RAM ID for K4UCE3Q4AB-MGCL Generate RAM ID for Samsung K4UCE3Q4AB-MGCL DRAM Part Name ID to assign K4UCE3Q4AB-MGCL 3 (0011) BUG=b:281950933 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I75818b8a34d010fc0efe90c7625162e40e3b0dca Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75156 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/mainboard/google/brya/variants/anahera/memory/Makefile.inc M src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tarun Tuli: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/anahera/memory/Makefile.inc b/src/mainboard/google/brya/variants/anahera/memory/Makefile.inc index b506c6f..00fd95a 100644 --- a/src/mainboard/google/brya/variants/anahera/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/anahera/memory/Makefile.inc @@ -7,5 +7,5 @@ SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL -SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE, H54G68CYRBX248 +SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE, H54G68CYRBX248, K4UCE3Q4AB-MGCL SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 4(0b0100) Parts = MT53E2G32D4NQ-046 WT:A, MT53E2G32D4NQ-046 WT:C diff --git a/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt index 2a8f8a7..d162828 100644 --- a/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt @@ -20,3 +20,4 @@ K4UBE3D4AB-MGCL 2 (0010) MT53E2G32D4NQ-046 WT:C 4 (0100) H54G68CYRBX248 3 (0011) +K4UCE3Q4AB-MGCL 3 (0011) diff --git a/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt index ab8700fc..361f875 100644 --- a/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt @@ -14,3 +14,4 @@ K4UBE3D4AB-MGCL MT53E2G32D4NQ-046 WT:C H54G68CYRBX248 +K4UCE3Q4AB-MGCL -- To view, visit https://review.coreboot.org/c/coreboot/+/75156?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75818b8a34d010fc0efe90c7625162e40e3b0dca Gerrit-Change-Number: 75156 Gerrit-PatchSet: 5 Gerrit-Owner: Chen Wisley <wisley.chen%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[master]: mb/google/brya/var/redrix: Generate RAM ID for K4UCE3Q4AB-MGCL
by Martin L Roth (Code Review) 03 Jun '23

03 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75155?usp=email ) Change subject: mb/google/brya/var/redrix: Generate RAM ID for K4UCE3Q4AB-MGCL ...................................................................... mb/google/brya/var/redrix: Generate RAM ID for K4UCE3Q4AB-MGCL Generate RAM ID for Samsung K4UCE3Q4AB-MGCL DRAM Part Name ID to assign K4UCE3Q4AB-MGCL 3 (0011) BUG=b:281943392 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I79b29b1195468272c7f64a0eeb15d032eff8c1d3 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75155 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/mainboard/google/brya/variants/redrix/memory/Makefile.inc M src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tarun Tuli: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc b/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc index e92b60c..f0d6e3d 100644 --- a/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc @@ -7,5 +7,5 @@ SPD_SOURCES += spd/lp4x/set-0/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL -SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE, H54G68CYRBX248 +SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE, H54G68CYRBX248, K4UCE3Q4AB-MGCL SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 4(0b0100) Parts = MT53E2G32D4NQ-046 WT:A, MT53E2G32D4NQ-046 WT:C diff --git a/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt index a277312..74768aa 100644 --- a/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt @@ -20,3 +20,4 @@ K4UBE3D4AB-MGCL 2 (0010) MT53E2G32D4NQ-046 WT:C 4 (0100) H54G68CYRBX248 3 (0011) +K4UCE3Q4AB-MGCL 3 (0011) diff --git a/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt index ab8700fc..361f875 100644 --- a/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt @@ -14,3 +14,4 @@ K4UBE3D4AB-MGCL MT53E2G32D4NQ-046 WT:C H54G68CYRBX248 +K4UCE3Q4AB-MGCL -- To view, visit https://review.coreboot.org/c/coreboot/+/75155?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79b29b1195468272c7f64a0eeb15d032eff8c1d3 Gerrit-Change-Number: 75155 Gerrit-PatchSet: 4 Gerrit-Owner: Chen Wisley <wisley.chen%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: spd/lp4x: Generate initial SPD for K4UCE3Q4AB-MGCL
by Martin L Roth (Code Review) 03 Jun '23

03 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75154?usp=email ) Change subject: spd/lp4x: Generate initial SPD for K4UCE3Q4AB-MGCL ...................................................................... spd/lp4x: Generate initial SPD for K4UCE3Q4AB-MGCL Generate initial SPD for Samsung K4UCE3Q4AB-MGCL BUG=b:281943392 BRANCH=firmware-brya-14505.B TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x Change-Id: I0a860f3f9c307e70f63a53435cc26e6f278d0a17 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75154 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M spd/lp4x/memory_parts.json M spd/lp4x/set-0/parts_spd_manifest.generated.txt M spd/lp4x/set-1/parts_spd_manifest.generated.txt 3 files changed, 15 insertions(+), 1 deletion(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/spd/lp4x/memory_parts.json b/spd/lp4x/memory_parts.json index f89951c..56c6d87 100644 --- a/spd/lp4x/memory_parts.json +++ b/spd/lp4x/memory_parts.json @@ -363,6 +363,18 @@ "ranksPerChannel": 2, "speedMbps": 4267 } - } + }, + { + "name": "K4UCE3Q4AB-MGCL", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 4, + "diesPerPackage": 2, + "bitWidthPerChannel": 8, + "ranksPerChannel": 2, + "speedMbps": 4267 + } + } ] } diff --git a/spd/lp4x/set-0/parts_spd_manifest.generated.txt b/spd/lp4x/set-0/parts_spd_manifest.generated.txt index 39b3152..4af8f6a7 100644 --- a/spd/lp4x/set-0/parts_spd_manifest.generated.txt +++ b/spd/lp4x/set-0/parts_spd_manifest.generated.txt @@ -31,3 +31,4 @@ K4UBE3D4AB-MGCL,spd-3.hex MT53E2G32D4NQ-046 WT:C,spd-7.hex H54G68CYRBX248,spd-2.hex +K4UCE3Q4AB-MGCL,spd-2.hex diff --git a/spd/lp4x/set-1/parts_spd_manifest.generated.txt b/spd/lp4x/set-1/parts_spd_manifest.generated.txt index 1cb2516..961a52e 100644 --- a/spd/lp4x/set-1/parts_spd_manifest.generated.txt +++ b/spd/lp4x/set-1/parts_spd_manifest.generated.txt @@ -31,3 +31,4 @@ K4UBE3D4AB-MGCL,spd-3.hex MT53E2G32D4NQ-046 WT:C,spd-10.hex H54G68CYRBX248,spd-2.hex +K4UCE3Q4AB-MGCL,spd-2.hex -- To view, visit https://review.coreboot.org/c/coreboot/+/75154?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a860f3f9c307e70f63a53435cc26e6f278d0a17 Gerrit-Change-Number: 75154 Gerrit-PatchSet: 4 Gerrit-Owner: Chen Wisley <wisley.chen%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: spd/lp4x: Generate initial SPD for K4UCE3Q4AB-MGCL
by Martin L Roth (Code Review) 03 Jun '23

03 Jun '23

Attention is currently required from: Chen Wisley, Nick Vaccaro, Tarun Tuli, YH Lin. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75154?usp=email ) Change subject: spd/lp4x: Generate initial SPD for K4UCE3Q4AB-MGCL ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75154?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a860f3f9c307e70f63a53435cc26e6f278d0a17 Gerrit-Change-Number: 75154 Gerrit-PatchSet: 3 Gerrit-Owner: Chen Wisley <wisley.chen%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Chen Wisley <wisley.chen%quantatw.com(a)gtempaccount.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Sat, 03 Jun 2023 20:36:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/starlabs/starbook: Fix the ramtop CMOS entry
by Martin L Roth (Code Review) 03 Jun '23

03 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75420?usp=email ) Change subject: mb/starlabs/starbook: Fix the ramtop CMOS entry ...................................................................... mb/starlabs/starbook: Fix the ramtop CMOS entry The ramtop entry has to be 10 bytes long, and it was incorrectly set to 10 bits, instead of 10 bytes. Change this to 80. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I506f9d98a389dd859038fd270c5e344b65f514f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75420 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/cmos.layout M src/mainboard/starlabs/starbook/variants/tgl/cmos.layout 2 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/cmos.layout b/src/mainboard/starlabs/starbook/cmos.layout index d725d04..c15c6f8 100644 --- a/src/mainboard/starlabs/starbook/cmos.layout +++ b/src/mainboard/starlabs/starbook/cmos.layout @@ -8,6 +8,9 @@ 0 120 r 0 reserved_memory # ----------------------------------------------------------------- +# coreboot config options: ramtop +304 80 h 0 ramtop + # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 2 boot_option 388 4 h 0 reboot_counter @@ -44,9 +47,6 @@ # coreboot config options: check sums 984 16 h 0 check_sum -# coreboot config options: ramtop -1000 10 h 0 ramtop - # Bank: 2 # embedded controller settings (outside the checksummed area) 1024 8 h 1 fn_lock_state diff --git a/src/mainboard/starlabs/starbook/variants/tgl/cmos.layout b/src/mainboard/starlabs/starbook/variants/tgl/cmos.layout index 589359f..b5a2fb7 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/cmos.layout +++ b/src/mainboard/starlabs/starbook/variants/tgl/cmos.layout @@ -8,6 +8,9 @@ 0 120 r 0 reserved_memory # ----------------------------------------------------------------- +# coreboot config options: ramtop +304 80 h 0 ramtop + # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 2 boot_option 388 4 h 0 reboot_counter @@ -44,9 +47,6 @@ # coreboot config options: check sums 984 16 h 0 check_sum -# coreboot config options: ramtop -1000 10 h 0 ramtop - # Bank: 2 # embedded controller settings (outside the checksummed area) 1024 8 h 1 fn_lock_state -- To view, visit https://review.coreboot.org/c/coreboot/+/75420?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I506f9d98a389dd859038fd270c5e344b65f514f8 Gerrit-Change-Number: 75420 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2023