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Hello Eric Lai, Ivy Jian, Kapil Porwal, Ronak Kanabar, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/meteorlake: Apply PCIe RP mask based on SoC type
......................................................................
soc/intel/meteorlake: Apply PCIe RP mask based on SoC type
This patch ensures to update the FSP-M UPDs related to PCIe RP mask
properly as per the SoC type.
For example: PCIe RPs belong to the SoC/IOE die for MTL-U/P whereelse
PCIe RPs are from PCH die in case of MTL-S.
BUG=b:276697173
TEST=Able to build and boot google/rex.
Change-Id: Ice81553274682476bb4c927061b1196dc142836d
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/meteorlake/romstage/fsp_params.c
1 file changed, 12 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/75608/3
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Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74483?usp=email )
Change subject: util/crossgcc/buildgcc: Drop some superfluous comments
......................................................................
Patch Set 1: Code-Review+1
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Change subject: soc/sifive: Comment out set but unused variables
......................................................................
Patch Set 1: Code-Review+2
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Change subject: arch/riscv: Always build opensbi with GCC
......................................................................
Patch Set 1: Code-Review+2
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