coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: soc/intel/alderlake: Allow using the microcode blob from the repo
by Felix Singer (Code Review) 03 Jun '23

03 Jun '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75632?usp=email ) Change subject: soc/intel/alderlake: Allow using the microcode blob from the repo ...................................................................... soc/intel/alderlake: Allow using the microcode blob from the repo Change-Id: I11c9cb13fa81118bfcb819bad5fb39731c7e3e76 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/75632/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 0e5a671..a1172dd 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -21,7 +21,6 @@ config SOC_INTEL_ALDERLAKE_PCH_N bool select SOC_INTEL_ALDERLAKE - select MICROCODE_BLOB_UNDISCLOSED help Choose this option if your mainboard has a PCH-N chipset. -- To view, visit https://review.coreboot.org/c/coreboot/+/75632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11c9cb13fa81118bfcb819bad5fb39731c7e3e76 Gerrit-Change-Number: 75632 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: 3rdparty/intel-microcode: Update submodule to upstream master
by Felix Singer (Code Review) 03 Jun '23

03 Jun '23

Felix Singer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/75631?usp=email ) Change subject: 3rdparty/intel-microcode: Update submodule to upstream master ...................................................................... 3rdparty/intel-microcode: Update submodule to upstream master Updating from commit id 2be47ed: 2023-02-14 17:52:48 -0600 - (microcode-20230214 Release) to commit id 9660518: 2023-05-17 14:50:35 -0600 - (microcode-20230516a Release) This brings in 3 new commits: 9660518 microcode-20230516a Release 05f5ca0 microcode-20230516 Release 752cd0a microcode-20230512 Release Change-Id: I52aa88f52392e489a6c863e02dc849c0236f36e1 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M 3rdparty/intel-microcode 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/75631/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75631?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52aa88f52392e489a6c863e02dc849c0236f36e1 Gerrit-Change-Number: 75631 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG
by Bernardo Perez Priego (Code Review) 03 Jun '23

03 Jun '23

Attention is currently required from: Jamie Ryu, Jay Patel, Kapil Porwal, Subrata Banik, Tarun Tuli, Wonkyu Kim. Hello Jamie Ryu, Jay Patel, Kapil Porwal, Subrata Banik, Tarun Tuli, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75525?usp=email to look at the new patch set (#6). Change subject: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG ...................................................................... mb/google/rex: Configure ISH GPIO's based on FW_CONFIG Configures ISH related GPIO's based on FW_CONFIG obtained from CBI. BUG=b:280329972,b:283023296 TEST= Set bit 21 of FW_CONFIG with CBI Boot rex board Check that ISH is enabled, loaded, and functional Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749 --- M src/mainboard/google/rex/variants/rex0/fw_config.c 1 file changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/75525/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/75525?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749 Gerrit-Change-Number: 75525 Gerrit-PatchSet: 6 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Jay Patel <jay2.patel(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG
by Bernardo Perez Priego (Code Review) 03 Jun '23

03 Jun '23

Attention is currently required from: Jamie Ryu, Jay Patel, Kapil Porwal, Subrata Banik, Tarun Tuli, Wonkyu Kim. Bernardo Perez Priego has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75525?usp=email ) Change subject: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/rex/variants/rex0/fw_config.c: https://review.coreboot.org/c/coreboot/+/75525/comment/30b4ac4b_95dcbbff : PS4, Line 37: ish_enable_pads > GPIOs, mentioned in b/283477280#comment3, are still missing. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75525?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749 Gerrit-Change-Number: 75525 Gerrit-PatchSet: 5 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Jay Patel <jay2.patel(a)intel.com> Gerrit-Comment-Date: Sat, 03 Jun 2023 03:58:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG
by Bernardo Perez Priego (Code Review) 03 Jun '23

03 Jun '23

Attention is currently required from: Bernardo Perez Priego, Jamie Ryu, Jay Patel, Subrata Banik, Tarun Tuli, Wonkyu Kim. Hello Jamie Ryu, Jay Patel, Kapil Porwal, Subrata Banik, Tarun Tuli, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75525?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG ...................................................................... mb/google/rex: Configure ISH GPIO's based on FW_CONFIG Configures ISH related GPIO's based on FW_CONFIG obtained from CBI. BUG=b:280329972,b:283023296 TEST= Set bit 21 of FW_CONFIG with CBI Boot rex board Check that ISH is enabled, loaded, and functional Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749 --- M src/mainboard/google/rex/variants/rex0/fw_config.c 1 file changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/75525/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/75525?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749 Gerrit-Change-Number: 75525 Gerrit-PatchSet: 5 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jay Patel <jay2.patel(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: Update intel-microcode submodule to upstream master
by Felix Singer (Code Review) 03 Jun '23

03 Jun '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75631?usp=email ) Change subject: Update intel-microcode submodule to upstream master ...................................................................... Update intel-microcode submodule to upstream master Updating from commit id 2be47ed: 2023-02-14 17:52:48 -0600 - (microcode-20230214 Release) to commit id 9660518: 2023-05-17 14:50:35 -0600 - (microcode-20230516a Release) This brings in 3 new commits: 9660518 microcode-20230516a Release 05f5ca0 microcode-20230516 Release 752cd0a microcode-20230512 Release Change-Id: I52aa88f52392e489a6c863e02dc849c0236f36e1 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M 3rdparty/intel-microcode 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/75631/1 diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 2be47ed..9660518 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 2be47edc99eeeb5b6d76bf9450b74747cdaf3263 +Subproject commit 9660518e90e72ba4ee4e654c943f8e4b02253a7b -- To view, visit https://review.coreboot.org/c/coreboot/+/75631?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52aa88f52392e489a6c863e02dc849c0236f36e1 Gerrit-Change-Number: 75631 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: vc/intel/fsp2: Drop Intel Quark FSP headers
by Felix Singer (Code Review) 03 Jun '23

03 Jun '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75630?usp=email ) Change subject: vc/intel/fsp2: Drop Intel Quark FSP headers ...................................................................... vc/intel/fsp2: Drop Intel Quark FSP headers Intel Quark was dropped in commit 531023285e. Thus, drop the remaining FSP headers. Change-Id: Ie3c11c6f68d879b944f7b4ed0fde0ee4aae204b9 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- D src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h D src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h D src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h D src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h 4 files changed, 0 insertions(+), 436 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/75630/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h deleted file mode 100644 index cfd1ac0..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include <FspEas.h> - -#pragma pack(push, 1) - -#define FSPT_UPD_SIGNATURE 0x545F4450554B5251 /* 'QRKUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554B5251 /* 'QRKUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554B5251 /* 'QRKUPD_S' */ - -#pragma pack(pop) - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h deleted file mode 100644 index 28e4d21..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h +++ /dev/null @@ -1,239 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include <FspUpd.h> - -#pragma pack(push, 1) - - -/** Fsp M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - RmuBaseAddress - RMU microcode binary base address in SPI flash' -**/ - UINT32 RmuBaseAddress; - -/** Offset 0x0044 - RmuLength - RMU microcode binary length in bytes -**/ - UINT32 RmuLength; - -/** Offset 0x0048 - SerialPortBaseAddress - Debug serial port base address set by BIOS. Zero disables debug serial output. -**/ - UINT32 Reserved_48; - -/** Offset 0x004C - tRAS - ACT to PRE command period in picoseconds. -**/ - UINT32 tRAS; - -/** Offset 0x0050 - tWTR - Delay from start of internal write transaction to internal read command in picoseconds. -**/ - UINT32 tWTR; - -/** Offset 0x0054 - tRRD - ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds. -**/ - UINT32 tRRD; - -/** Offset 0x0058 - tFAW - Four activate window (JESD79 specific to page size 1K/2K) in picoseconds. -**/ - UINT32 tFAW; - -/** Offset 0x005C - Flags - Bitmap of MRC_FLAG_XXX: ECC_EN BIT0, SCRAMBLE_EN BIT1, MEMTEST_EN - BIT2, TOP_TREE_EN BIT3 0b DDR "fly-by" topology else 1b DDR "tree" - topology, WR_ODT_EN BIT4 If set ODR signal is asserted to DRAM devices - on writes. -**/ - UINT32 Flags; - -/** Offset 0x0060 - DramWidth - 0=x8, 1=x16, others=RESERVED. -**/ - UINT8 DramWidth; - -/** Offset 0x0061 - DramSpeed - 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory. -**/ - UINT8 DramSpeed; - -/** Offset 0x0062 - DramType - 0=DDR3, 1=DDR3L, others=RESERVED. -**/ - UINT8 DramType; - -/** Offset 0x0063 - RankMask - bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED. -**/ - UINT8 RankMask; - -/** Offset 0x0064 - ChanMask - bit[0] CHAN0_EN, others=RESERVED. -**/ - UINT8 ChanMask; - -/** Offset 0x0065 - ChanWidth - 1=x16, others=RESERVED. -**/ - UINT8 ChanWidth; - -/** Offset 0x0066 - AddrMode - 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED. -**/ - UINT8 AddrMode; - -/** Offset 0x0067 - SrInt - 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE. -**/ - UINT8 SrInt; - -/** Offset 0x0068 - SrTemp - 0=normal, 1=extended, others=RESERVED. -**/ - UINT8 SrTemp; - -/** Offset 0x0069 - DramRonVal - 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control. -**/ - UINT8 DramRonVal; - -/** Offset 0x006A - DramRttNomVal - 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED. -**/ - UINT8 DramRttNomVal; - -/** Offset 0x006B - DramRttWrVal - 0=off others=RESERVED. -**/ - UINT8 DramRttWrVal; - -/** Offset 0x006C - SocRdOdtVal - 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED. -**/ - UINT8 SocRdOdtVal; - -/** Offset 0x006D - SocWrRonVal - 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED. -**/ - UINT8 SocWrRonVal; - -/** Offset 0x006E - SocWrSlewRate - 0=2.5V/ns, 1=4V/ns, others=RESERVED. -**/ - UINT8 SocWrSlewRate; - -/** Offset 0x006F - DramDensity - 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED. -**/ - UINT8 DramDensity; - -/** Offset 0x0070 - tCL - DRAM CAS Latency in clocks -**/ - UINT8 tCL; - -/** Offset 0x0071 - EccScrubInterval - ECC scrub interval in miliseconds 1..255 (0 works as feature disable -**/ - UINT8 EccScrubInterval; - -/** Offset 0x0072 - EccScrubBlkSize - Number of 32B blocks read for ECC scrub 2..16 -**/ - UINT8 EccScrubBlkSize; - -/** Offset 0x0073 - SmmTsegSize - Size of the SMM region in 1 MiB chunks -**/ - UINT8 SmmTsegSize; - -/** Offset 0x0074 - FspReservedMemoryLength - FSP reserved memory length in bytes -**/ - UINT32 FspReservedMemoryLength; - -/** Offset 0x0078 - MrcDataPtr - Pointer to saved MRC data -**/ - UINT32 MrcDataPtr; - -/** Offset 0x007C - MrcDataLength - Length of saved MRC data -**/ - UINT32 MrcDataLength; - -/** Offset 0x0080 -**/ - UINT32 SerialPortPollForChar; - -/** Offset 0x0084 -**/ - UINT32 SerialPortReadChar; - -/** Offset 0x0088 -**/ - UINT32 SerialPortWriteChar; - -/** Offset 0x008C -**/ - UINT16 UpdTerminator; -} FSP_M_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSP_M_CONFIG FspmConfig; -} FSPM_UPD; - -#pragma pack(pop) - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h deleted file mode 100644 index a613000..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h +++ /dev/null @@ -1,56 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include <FspUpd.h> - -#pragma pack(push, 1) - - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack(pop) - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h deleted file mode 100644 index 02a1e09..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h +++ /dev/null @@ -1,93 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include <FspUpd.h> - -#pragma pack(push, 1) - - -/** Fsp T Common UPD -**/ -typedef struct { - -/** Offset 0x0020 -**/ - UINT8 Revision; - -/** Offset 0x0021 -**/ - UINT8 Reserved[3]; - -/** Offset 0x0024 -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0028 -**/ - UINT32 MicrocodeRegionLength; - -/** Offset 0x002C -**/ - UINT32 CodeRegionBase; - -/** Offset 0x0030 -**/ - UINT32 CodeRegionLength; - -/** Offset 0x0034 -**/ - UINT8 Reserved1[12]; -} FSPT_COMMON_UPD; - -/** Fsp T UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPT_COMMON_UPD FsptCommonUpd; - -/** Offset 0x0040 -**/ - UINT16 UpdTerminator; -} FSPT_UPD; - -#pragma pack(pop) - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/75630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3c11c6f68d879b944f7b4ed0fde0ee4aae204b9 Gerrit-Change-Number: 75630 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: vc/intel/fsp/mtl: Update header files from 3165_81 to 3194_81
by Felix Singer (Code Review) 03 Jun '23

03 Jun '23

Attention is currently required from: Kilari Raasi, Martin L Roth, Paul Menzel, Ronak Kanabar, Subrata Banik. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75519?usp=email ) Change subject: vc/intel/fsp/mtl: Update header files from 3165_81 to 3194_81 ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75519?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43f276e9b8e46edc76dc7749d2a610cfa836a718 Gerrit-Change-Number: 75519 Gerrit-PatchSet: 10 Gerrit-Owner: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Sat, 03 Jun 2023 03:07:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt
by Felix Held (Code Review) 03 Jun '23

03 Jun '23

Attention is currently required from: Arthur Heymans, Fred Reitberger, Jason Glenesk, Matt DeVillier, Nico Huber, Raul Rangel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74843?usp=email ) Change subject: soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt ...................................................................... Patch Set 14: (1 comment) File src/soc/amd/common/block/data_fabric/domain.c: https://review.coreboot.org/c/coreboot/+/74843/comment/17b96ed2_193f805a : PS11, Line 169: if (base > PCI_IO_CONFIG_LAST_PORT || limit < PCI_IO_CONFIG_INDEX) { > read that part of the spec and it looks like a dword io producer resource should just work. […] tested with https://review.coreboot.org/c/coreboot/+/75613/2 applied which i then removed form the patch train du to it not working properly in the linux case. windows 10 doesn't care if it's a word or dword io resource type; the kernel from ubuntu 2022.4 doesn't like the dword io resource type much though: acpi PNP0A08:00: host bridge window expanded to [io 0x0000-0xffff]; [io 0x0000-0xffff window] ignored at least it doesn't fail like in the case with the length field being truncated to 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/74843?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf6d38a8ef5bb0163c4d1c021bf892c323d9a448 Gerrit-Change-Number: 74843 Gerrit-PatchSet: 14 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Sat, 03 Jun 2023 01:09:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt
by Felix Held (Code Review) 03 Jun '23

03 Jun '23

Attention is currently required from: Arthur Heymans, Fred Reitberger, Jason Glenesk, Matt DeVillier, Nico Huber, Raul Rangel. Hello Arthur Heymans, Fred Reitberger, Jason Glenesk, Matt DeVillier, Nico Huber, Raul Rangel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74843?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins) Change subject: soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt ...................................................................... soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt Generate the PCI0 _CRS ACPI resource template to tell the OS which PCI bus numbers and IO and MMIO regions can be used for PCI devices below _SB/PCI0. This data corresponds to what amd_pci_domain_scan_bus and amd_pci_domain_read_resources provided to the resource allocator. This makes sure that the PCI0 _CRS ACPI resource template matches the constraints the resource allocator used when allocating resources. TEST=With also the rest of the current patch train applied, the generated _CRS resource template contains the expected PCI bus numbers and IO and MMIO resources and both Linux and Windows boot on Mandolin. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iaf6d38a8ef5bb0163c4d1c021bf892c323d9a448 --- M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/common/block/include/amdblocks/data_fabric.h 2 files changed, 94 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/74843/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/74843?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf6d38a8ef5bb0163c4d1c021bf892c323d9a448 Gerrit-Change-Number: 74843 Gerrit-PatchSet: 14 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2023