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Change subject: Docs: Update sphinx targets with the build directory
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Patch Set 1: Code-Review+2
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Change subject: cpu/x86/smm: Don't save EFER
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Patch Set 13: Code-Review+2
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Change subject: cpu/x86/smm: Drop fxsave/fxrstor logic
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Patch Set 7: Code-Review+2
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Change subject: lib/dimm_info_util.c: Add newlines to log messages
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Patch Set 1: Code-Review+2
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Change subject: 3rdparty/intel-microcode: Update submodule to upstream master
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Patch Set 2: Code-Review+2
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Change subject: vc/intel/fsp/mtl: Update header files from 3165_81 to 3194_81
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
will hold this Cl unless other FSP Cls lands
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Hello Subrata Banik, Tarun Tuli,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: [WIP] soc/intel/alderlake: Allow using IOT FSP from repo for PCH type N
......................................................................
[WIP] soc/intel/alderlake: Allow using IOT FSP from repo for PCH type N
Change-Id: I57b54653bd29a728825210403c8f426eb1c9cc48
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/75633/2
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Hello Subrata Banik, Tarun Tuli,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75632?usp=email
to look at the new patch set (#2).
Change subject: [WIP] soc/intel/alderlake: Allow using the microcode blob from the repo
......................................................................
[WIP] soc/intel/alderlake: Allow using the microcode blob from the repo
Change-Id: I11c9cb13fa81118bfcb819bad5fb39731c7e3e76
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/75632/2
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Change subject: soc/intel/alderlake: Allow using IOT FSP from repo for PCH type N
......................................................................
soc/intel/alderlake: Allow using IOT FSP from repo for PCH type N
Change-Id: I57b54653bd29a728825210403c8f426eb1c9cc48
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/75633/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index a1172dd..5d16b14 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -20,6 +20,7 @@
config SOC_INTEL_ALDERLAKE_PCH_N
bool
+ select HAVE_INTEL_FSP_REPO
select SOC_INTEL_ALDERLAKE
help
Choose this option if your mainboard has a PCH-N chipset.
@@ -397,12 +398,12 @@
config FSP_HEADER_PATH
string "Location of FSP headers"
- default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N
default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if SOC_INTEL_RAPTORLAKE
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT
default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P
default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S
+ default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Include/" if SOC_INTEL_ALDERLAKE_PCH_N
default "src/vendorcode/intel/fsp/fsp2_0/alderlake/"
config FSP_FD_PATH
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