coreboot-gerrit June 2023

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[S] Change in coreboot[master]: soc/intel/meteorlake: Introduce different SoC flavors of Meteor Lake
by Subrata Banik (Code Review) 04 Jun '23

04 Jun '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75606?usp=email ) Change subject: soc/intel/meteorlake: Introduce different SoC flavors of Meteor Lake ...................................................................... soc/intel/meteorlake: Introduce different SoC flavors of Meteor Lake This patch introduces the different SoC flavors of Intel Meteor Lake as: * MTL-U * MTL-P * MTL-S MTL-U and MTL-P are PCH less designs, while MTL-S is with PCH die. The task for mainboard is to specify the correct SoC type rather than selecting the MTL SoC by default. This change is necessary to support the different SoC flavors of Intel Meteor Lake. BUG=b:276697173 TEST=Able to build and boot google/rex. Change-Id: I27404bbbd0b489412953118e140f6f39b6e43426 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75606 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 17 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved Tarun Tuli: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index db347af..3f7f883 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -1,7 +1,23 @@ config SOC_INTEL_METEORLAKE bool help - Intel Meteorlake support + Intel Meteorlake support. Mainboards should specify the SoC + type using the `SOC_INTEL_METEORLAKE_*` options instead + of selecting this option directly. + +config SOC_INTEL_METEORLAKE_U_P + bool + select SOC_INTEL_METEORLAKE + help + Choose this option if your mainboard has a MTL-U (15W) or MTL-P (28W) SoC. + Note, MTL-U/P SoC combines Compute, GFX, SoC and IOE die. + +config SOC_INTEL_METEORLAKE_S + bool + select SOC_INTEL_METEORLAKE + help + Choose this option if your mainboard has a MTL-S (45W) SoC. + Note, MTL-S SoC combines Compute, GFX, SoC, IOE and PCH die. if SOC_INTEL_METEORLAKE -- To view, visit https://review.coreboot.org/c/coreboot/+/75606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27404bbbd0b489412953118e140f6f39b6e43426 Gerrit-Change-Number: 75606 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/intel/meteorlake: Hook up UPD PchHdaSdiEnable
by Subrata Banik (Code Review) 04 Jun '23

04 Jun '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75529?usp=email ) Change subject: soc/intel/meteorlake: Hook up UPD PchHdaSdiEnable ...................................................................... soc/intel/meteorlake: Hook up UPD PchHdaSdiEnable Hook the PchHdaSdiEnable UPD so that mainboard can change the settings via devicetree. PchHdaSdiEnable UPD enable HDA SDI lanes. BUG=b:273962021 TEST=Verified the settings on google/rex using debug FSP logs. Change-Id: I43f1e59d28fc07218f8e25266f8ce3bdcf3f6e5c Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75529 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/romstage/fsp_params.c 2 files changed, 7 insertions(+), 0 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Tarun Tuli: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index acb3738..37a7615 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -19,6 +19,7 @@ #include <stdint.h> #define MAX_SAGV_POINTS 4 +#define MAX_HD_AUDIO_SDI_LINKS 2 /* Types of different SKUs */ enum soc_intel_meteorlake_power_limits { @@ -192,6 +193,8 @@ /* Audio related */ uint8_t pch_hda_dsp_enable; + bool pch_hda_sdi_enable[MAX_HD_AUDIO_SDI_LINKS]; + /* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */ enum { HDA_TMODE_2T = 0, diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 171009f..0173060 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -223,6 +223,10 @@ m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode; m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency; m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable; + + for (int i = 0; i < MAX_HD_AUDIO_SDI_LINKS; i++) + m_cfg->PchHdaSdiEnable[i] = config->pch_hda_sdi_enable[i]; + /* * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to * configure GPIO pads for audio. Mainboard is expected to perform all GPIO -- To view, visit https://review.coreboot.org/c/coreboot/+/75529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43f1e59d28fc07218f8e25266f8ce3bdcf3f6e5c Gerrit-Change-Number: 75529 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/intel/meteorlake: Hook up UPD PchHdaSdiEnable
by Subrata Banik (Code Review) 04 Jun '23

04 Jun '23

Attention is currently required from: Eric Lai, Himanshu Sahdev, Paul Menzel, Ronak Kanabar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75529?usp=email ) Change subject: soc/intel/meteorlake: Hook up UPD PchHdaSdiEnable ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43f1e59d28fc07218f8e25266f8ce3bdcf3f6e5c Gerrit-Change-Number: 75529 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Sun, 04 Jun 2023 18:18:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: vc/intel/fsp/mtl: Update header files from 3165_81 to 3194_81
by Subrata Banik (Code Review) 04 Jun '23

04 Jun '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75519?usp=email ) Change subject: vc/intel/fsp/mtl: Update header files from 3165_81 to 3194_81 ...................................................................... vc/intel/fsp/mtl: Update header files from 3165_81 to 3194_81 Update header files for FSP for Meteor Lake platform to version 3194_81, previous version being 3165_81. FSPM: 1. Add 'PchPcieRpEnableMask' UPD 2. Address offset changes Add "FspProducerDataHeader.h" file to support MRC version Info BUG=b:284803304 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I43f276e9b8e46edc76dc7749d2a610cfa836a718 Signed-off-by: Kilari Raasi <kilari.raasi(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75519 Reviewed-by: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- A src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspProducerDataHeader.h M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h 2 files changed, 88 insertions(+), 4 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Himanshu Sahdev: Looks good to me, but someone else must approve Felix Singer: Looks good to me, approved build bot (Jenkins): Verified Tarun Tuli: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspProducerDataHeader.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspProducerDataHeader.h new file mode 100644 index 0000000..aa96b3a --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspProducerDataHeader.h @@ -0,0 +1,78 @@ +/** @file + + Copyright (c) 2023, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ +#ifndef _FSP_PRODUCER_DATA_HEADER_H_ +#define _FSP_PRODUCER_DATA_HEADER_H_ + +#include <Guid/FspHeaderFile.h> + +// +// FSP Header Data structure from FspHeader driver. +// +#pragma pack(1) +/// +/// FSP Producer Data Subtype - 1 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of RC version which is used to build this FSP image. + /// + UINT32 RcVersion; + /// + /// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM". + /// + UINT8 BuildTimeStamp[BUILD_TIME_STAMP_SIZE]; +} FSP_PRODUCER_DATA_TYPE1; + +/// +/// FSP Producer Data Subtype - 2 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image. + /// + UINT8 MrcVersion [4]; +} FSP_PRODUCER_DATA_TYPE2; + +typedef struct { + FSP_INFO_HEADER FspInfoHeader; + FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader; + FSP_PRODUCER_DATA_TYPE1 FspProduceDataType1; + FSP_PRODUCER_DATA_TYPE2 FspProduceDataType2; + FSP_PATCH_TABLE FspPatchTable; +} FSP_PRODUCER_DATA_TABLES; +#pragma pack() + +#endif // _FSP_PRODUCER_DATA_HEADER_H diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h index ac6b6c7..f8edff8 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h @@ -1740,7 +1740,13 @@ /** Offset 0x0AB9 - Reserved **/ - UINT8 Reserved39[59]; + UINT8 Reserved39[55]; + +/** Offset 0x0AF0 - Enable PCH PCIE RP Mask + Enable/disable PCH PCIE Root Ports. 0: disable, 1: enable. One bit for each port, + bit0 for port1, bit1 for port2, and so on. +**/ + UINT32 PchPcieRpEnableMask; /** Offset 0x0AF4 - Enable SOC/IOE PCIE RP Mask Enable/disable SOC/IOE PCIE Root Ports. 0: disable, 1: enable. One bit for each @@ -2998,7 +3004,7 @@ /** Offset 0x0DEC - Reserved **/ - UINT8 Reserved78[172]; + UINT8 Reserved78[188]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -3017,11 +3023,11 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0E98 +/** Offset 0x0EA8 **/ UINT8 Rsvd500[6]; -/** Offset 0x0E9E +/** Offset 0x0EAE **/ UINT16 UpdTerminator; } FSPM_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/75519?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43f276e9b8e46edc76dc7749d2a610cfa836a718 Gerrit-Change-Number: 75519 Gerrit-PatchSet: 11 Gerrit-Owner: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: vc/intel/fsp/mtl: Update header files from 3165_81 to 3194_81
by Subrata Banik (Code Review) 04 Jun '23

04 Jun '23

Attention is currently required from: Kilari Raasi, Martin L Roth, Paul Menzel, Ronak Kanabar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75519?usp=email ) Change subject: vc/intel/fsp/mtl: Update header files from 3165_81 to 3194_81 ...................................................................... Patch Set 10: Code-Review+2 (1 comment) Patchset: PS10: > will hold this Cl unless other FSP Cls lands Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/75519?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43f276e9b8e46edc76dc7749d2a610cfa836a718 Gerrit-Change-Number: 75519 Gerrit-PatchSet: 10 Gerrit-Owner: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Sun, 04 Jun 2023 18:18:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/meteorlake: Hook up UPD PchHdaSdiEnable
by Subrata Banik (Code Review) 04 Jun '23

04 Jun '23

Attention is currently required from: Eric Lai, Himanshu Sahdev, Paul Menzel, Ronak Kanabar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75529?usp=email ) Change subject: soc/intel/meteorlake: Hook up UPD PchHdaSdiEnable ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/meteorlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/75529/comment/b83d6fad_1584425b : PS5, Line 228: m_cfg->PchHdaSdiEnable[i] = config->pch_hda_sdi_enable[i]; > im okay either way. i think this code is clearer than the memcpy and shouldnt be any appreciable performance difference given the few elements. i agree. marking it resolved now -- To view, visit https://review.coreboot.org/c/coreboot/+/75529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43f1e59d28fc07218f8e25266f8ce3bdcf3f6e5c Gerrit-Change-Number: 75529 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Sun, 04 Jun 2023 18:17:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/meteorlake: Fill PCI SSID parameters
by Kapil Porwal (Code Review) 04 Jun '23

04 Jun '23

Attention is currently required from: Subrata Banik, Tarun Tuli. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71643?usp=email ) Change subject: soc/intel/meteorlake: Fill PCI SSID parameters ...................................................................... Patch Set 5: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/71643?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I364c2052984b6f562bffe8f5ad7035c8b659d369 Gerrit-Change-Number: 71643 Gerrit-PatchSet: 5 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Sun, 04 Jun 2023 17:20:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Apply PCIe RP mask based on SoC type
by Kapil Porwal (Code Review) 04 Jun '23

04 Jun '23

Attention is currently required from: Ivy Jian, Paul Menzel, Ronak Kanabar, Subrata Banik, Tarun Tuli. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75608?usp=email ) Change subject: soc/intel/meteorlake: Apply PCIe RP mask based on SoC type ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75608?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice81553274682476bb4c927061b1196dc142836d Gerrit-Change-Number: 75608 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Sun, 04 Jun 2023 17:18:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/intel/mtlrvp: Select SOC_INTEL_METEORLAKE_U_P
by Kapil Porwal (Code Review) 04 Jun '23

04 Jun '23

Attention is currently required from: Ivy Jian, Subrata Banik. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75607?usp=email ) Change subject: mb/intel/mtlrvp: Select SOC_INTEL_METEORLAKE_U_P ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75607?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b1dec47ef9d12ac50317b86c4f0bc5fbe4e4dc3 Gerrit-Change-Number: 75607 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Sun, 04 Jun 2023 17:17:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex: Select SOC_INTEL_METEORLAKE_U_P
by Kapil Porwal (Code Review) 04 Jun '23

04 Jun '23

Attention is currently required from: Subrata Banik, Tarun Tuli. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75612?usp=email ) Change subject: mb/google/rex: Select SOC_INTEL_METEORLAKE_U_P ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75612?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c233e0a8ce58998dc1a0379662e386f9b3d0073 Gerrit-Change-Number: 75612 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Sun, 04 Jun 2023 17:16:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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