coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: mb/google/myst: Enable S0ix
by Martin L Roth (Code Review) 04 Jun '23

04 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74279?usp=email ) Change subject: mb/google/myst: Enable S0ix ...................................................................... mb/google/myst: Enable S0ix Enable s0ix on Myst. BUG=b:277215113 TEST=builds Change-Id: I3cabc2c3ba75f4490da18b861ef2b82ce240860d Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74279 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/myst/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Raul Rangel: Looks good to me, approved Eric Lai: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb index 7adb365..058f873 100644 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -83,6 +83,7 @@ register "gpp_clk_config[6]" = "GPP_CLK_OFF" # WWAN_AUX_RST_L GPIO register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO(b/277214353): reenable when PSPP works + register "s0ix_enable" = "true" device domain 0 on device ref gpp_bridge_2_1 on end # WWAN -- To view, visit https://review.coreboot.org/c/coreboot/+/74279?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cabc2c3ba75f4490da18b861ef2b82ce240860d Gerrit-Change-Number: 74279 Gerrit-PatchSet: 21 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: libpayload/uhci: Return expected length for control/bulk transfers
by Martin L Roth (Code Review) 04 Jun '23

04 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75349?usp=email ) Change subject: libpayload/uhci: Return expected length for control/bulk transfers ...................................................................... libpayload/uhci: Return expected length for control/bulk transfers Libpayload's USB API was changed in commit e9738dbe2b (libpayload: Make USB transfer functions return amount of bytes). However, the UHCI driver was never adapted. Instead of returning 0 for success, we can return the expected data length as a best effort. We won't be able to catch short transfers this way, but previously working cases will work again. Change-Id: I31d7de495a46af401e2cbe5a3b8f6349facad8ff Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75349 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/drivers/usb/uhci.c 1 file changed, 13 insertions(+), 11 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c index 538107e..eb252cd 100644 --- a/payloads/libpayload/drivers/usb/uhci.c +++ b/payloads/libpayload/drivers/usb/uhci.c @@ -310,7 +310,7 @@ } static int -uhci_control(usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen, +uhci_control(usbdev_t *dev, direction_t dir, int drlen, void *devreq, const int dalen, unsigned char *data) { int endp = 0; /* this is control: always 0 */ @@ -339,6 +339,7 @@ TD_STATUS_ACTIVE; int toggle = 1; + int len_left = dalen; for (i = 1; i < count; i++) { switch (dir) { case SETUP: tds[i].token = UHCI_SETUP; break; @@ -347,14 +348,14 @@ } tds[i].token |= dev->address << TD_DEVADDR_SHIFT | endp << TD_EP_SHIFT | - maxlen(min(mlen, dalen)) << TD_MAXLEN_SHIFT | + maxlen(min(mlen, len_left)) << TD_MAXLEN_SHIFT | toggle << TD_TOGGLE_SHIFT; tds[i].bufptr = virt_to_phys(data); tds[i].ctrlsts = (3 << TD_COUNTER_SHIFT) | (dev->speed?TD_LOWSPEED:0) | TD_STATUS_ACTIVE; toggle ^= 1; - dalen -= mlen; + len_left -= mlen; data += mlen; } @@ -374,7 +375,7 @@ qh_data); int result; if (td == 0) { - result = 0; + result = dalen; /* TODO: We should return the actually transferred length. */ } else { usb_debug("control packet, req %x\n", req); td_dump(td); @@ -438,25 +439,26 @@ /* finalize == 1: if data is of packet aligned size, add a zero length packet */ static int -uhci_bulk(endpoint_t *ep, int size, u8 *data, int finalize) +uhci_bulk(endpoint_t *ep, const int dalen, u8 *data, int finalize) { int maxpsize = ep->maxpacketsize; if (maxpsize == 0) fatal("MaxPacketSize == 0!!!"); - int numpackets = (size + maxpsize - 1) / maxpsize; - if (finalize && ((size % maxpsize) == 0)) { + int numpackets = (dalen + maxpsize - 1) / maxpsize; + if (finalize && ((dalen % maxpsize) == 0)) { numpackets++; } if (numpackets == 0) return 0; td_t *tds = create_schedule(numpackets); int i = 0, toggle = ep->toggle; - while ((size > 0) || ((size == 0) && (finalize != 0))) { - fill_schedule(&tds[i], ep, min(size, maxpsize), data, + int len_left = dalen; + while ((len_left > 0) || ((len_left == 0) && (finalize != 0))) { + fill_schedule(&tds[i], ep, min(len_left, maxpsize), data, &toggle); i++; data += maxpsize; - size -= maxpsize; + len_left -= maxpsize; } if (run_schedule(ep->dev, tds) == 1) { free(tds); @@ -464,7 +466,7 @@ } ep->toggle = toggle; free(tds); - return 0; + return dalen; /* TODO: We should return the actually transferred length. */ } typedef struct { -- To view, visit https://review.coreboot.org/c/coreboot/+/75349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31d7de495a46af401e2cbe5a3b8f6349facad8ff Gerrit-Change-Number: 75349 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/intel/apollolake: Select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B
by Martin L Roth (Code Review) 04 Jun '23

04 Jun '23

Attention is currently required from: Angel Pons, Michał Żygowski. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72072?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/apollolake: Select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/72072/comment/5a87f71c_829911a9 : PS3, Line 10: seletion same as last patch: 'selection' -- To view, visit https://review.coreboot.org/c/coreboot/+/72072?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If182e1285ad6bd3f7c54760440010c50f57f7013 Gerrit-Change-Number: 72072 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 04 Jun 2023 18:47:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B
by Martin L Roth (Code Review) 04 Jun '23

04 Jun '23

Attention is currently required from: Angel Pons, Maximilian Brune, Michał Żygowski, Paul Menzel. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69870?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69870/comment/579723bb_f04ad6aa : PS5, Line 10: rate seletion unlike other chipsets which use GEN_PMCON_A. Introduce new nit: selection -- To view, visit https://review.coreboot.org/c/coreboot/+/69870?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11241836ecc9066d323977b030686567c87ed256 Gerrit-Change-Number: 69870 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 04 Jun 2023 18:46:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: vc/intel/fsp2: Drop Intel Quark FSP headers
by Felix Singer (Code Review) 04 Jun '23

04 Jun '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75630?usp=email ) Change subject: vc/intel/fsp2: Drop Intel Quark FSP headers ...................................................................... vc/intel/fsp2: Drop Intel Quark FSP headers Intel Quark was dropped in commit 531023285e. Thus, drop the remaining FSP headers. Change-Id: Ie3c11c6f68d879b944f7b4ed0fde0ee4aae204b9 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75630 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- D src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h D src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h D src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h D src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h 4 files changed, 0 insertions(+), 436 deletions(-) Approvals: Elyes Haouas: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h deleted file mode 100644 index cfd1ac0..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include <FspEas.h> - -#pragma pack(push, 1) - -#define FSPT_UPD_SIGNATURE 0x545F4450554B5251 /* 'QRKUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554B5251 /* 'QRKUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554B5251 /* 'QRKUPD_S' */ - -#pragma pack(pop) - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h deleted file mode 100644 index 28e4d21..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h +++ /dev/null @@ -1,239 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include <FspUpd.h> - -#pragma pack(push, 1) - - -/** Fsp M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - RmuBaseAddress - RMU microcode binary base address in SPI flash' -**/ - UINT32 RmuBaseAddress; - -/** Offset 0x0044 - RmuLength - RMU microcode binary length in bytes -**/ - UINT32 RmuLength; - -/** Offset 0x0048 - SerialPortBaseAddress - Debug serial port base address set by BIOS. Zero disables debug serial output. -**/ - UINT32 Reserved_48; - -/** Offset 0x004C - tRAS - ACT to PRE command period in picoseconds. -**/ - UINT32 tRAS; - -/** Offset 0x0050 - tWTR - Delay from start of internal write transaction to internal read command in picoseconds. -**/ - UINT32 tWTR; - -/** Offset 0x0054 - tRRD - ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds. -**/ - UINT32 tRRD; - -/** Offset 0x0058 - tFAW - Four activate window (JESD79 specific to page size 1K/2K) in picoseconds. -**/ - UINT32 tFAW; - -/** Offset 0x005C - Flags - Bitmap of MRC_FLAG_XXX: ECC_EN BIT0, SCRAMBLE_EN BIT1, MEMTEST_EN - BIT2, TOP_TREE_EN BIT3 0b DDR "fly-by" topology else 1b DDR "tree" - topology, WR_ODT_EN BIT4 If set ODR signal is asserted to DRAM devices - on writes. -**/ - UINT32 Flags; - -/** Offset 0x0060 - DramWidth - 0=x8, 1=x16, others=RESERVED. -**/ - UINT8 DramWidth; - -/** Offset 0x0061 - DramSpeed - 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory. -**/ - UINT8 DramSpeed; - -/** Offset 0x0062 - DramType - 0=DDR3, 1=DDR3L, others=RESERVED. -**/ - UINT8 DramType; - -/** Offset 0x0063 - RankMask - bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED. -**/ - UINT8 RankMask; - -/** Offset 0x0064 - ChanMask - bit[0] CHAN0_EN, others=RESERVED. -**/ - UINT8 ChanMask; - -/** Offset 0x0065 - ChanWidth - 1=x16, others=RESERVED. -**/ - UINT8 ChanWidth; - -/** Offset 0x0066 - AddrMode - 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED. -**/ - UINT8 AddrMode; - -/** Offset 0x0067 - SrInt - 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE. -**/ - UINT8 SrInt; - -/** Offset 0x0068 - SrTemp - 0=normal, 1=extended, others=RESERVED. -**/ - UINT8 SrTemp; - -/** Offset 0x0069 - DramRonVal - 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control. -**/ - UINT8 DramRonVal; - -/** Offset 0x006A - DramRttNomVal - 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED. -**/ - UINT8 DramRttNomVal; - -/** Offset 0x006B - DramRttWrVal - 0=off others=RESERVED. -**/ - UINT8 DramRttWrVal; - -/** Offset 0x006C - SocRdOdtVal - 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED. -**/ - UINT8 SocRdOdtVal; - -/** Offset 0x006D - SocWrRonVal - 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED. -**/ - UINT8 SocWrRonVal; - -/** Offset 0x006E - SocWrSlewRate - 0=2.5V/ns, 1=4V/ns, others=RESERVED. -**/ - UINT8 SocWrSlewRate; - -/** Offset 0x006F - DramDensity - 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED. -**/ - UINT8 DramDensity; - -/** Offset 0x0070 - tCL - DRAM CAS Latency in clocks -**/ - UINT8 tCL; - -/** Offset 0x0071 - EccScrubInterval - ECC scrub interval in miliseconds 1..255 (0 works as feature disable -**/ - UINT8 EccScrubInterval; - -/** Offset 0x0072 - EccScrubBlkSize - Number of 32B blocks read for ECC scrub 2..16 -**/ - UINT8 EccScrubBlkSize; - -/** Offset 0x0073 - SmmTsegSize - Size of the SMM region in 1 MiB chunks -**/ - UINT8 SmmTsegSize; - -/** Offset 0x0074 - FspReservedMemoryLength - FSP reserved memory length in bytes -**/ - UINT32 FspReservedMemoryLength; - -/** Offset 0x0078 - MrcDataPtr - Pointer to saved MRC data -**/ - UINT32 MrcDataPtr; - -/** Offset 0x007C - MrcDataLength - Length of saved MRC data -**/ - UINT32 MrcDataLength; - -/** Offset 0x0080 -**/ - UINT32 SerialPortPollForChar; - -/** Offset 0x0084 -**/ - UINT32 SerialPortReadChar; - -/** Offset 0x0088 -**/ - UINT32 SerialPortWriteChar; - -/** Offset 0x008C -**/ - UINT16 UpdTerminator; -} FSP_M_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSP_M_CONFIG FspmConfig; -} FSPM_UPD; - -#pragma pack(pop) - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h deleted file mode 100644 index a613000..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h +++ /dev/null @@ -1,56 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include <FspUpd.h> - -#pragma pack(push, 1) - - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack(pop) - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h deleted file mode 100644 index 02a1e09..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h +++ /dev/null @@ -1,93 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include <FspUpd.h> - -#pragma pack(push, 1) - - -/** Fsp T Common UPD -**/ -typedef struct { - -/** Offset 0x0020 -**/ - UINT8 Revision; - -/** Offset 0x0021 -**/ - UINT8 Reserved[3]; - -/** Offset 0x0024 -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0028 -**/ - UINT32 MicrocodeRegionLength; - -/** Offset 0x002C -**/ - UINT32 CodeRegionBase; - -/** Offset 0x0030 -**/ - UINT32 CodeRegionLength; - -/** Offset 0x0034 -**/ - UINT8 Reserved1[12]; -} FSPT_COMMON_UPD; - -/** Fsp T UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPT_COMMON_UPD FsptCommonUpd; - -/** Offset 0x0040 -**/ - UINT16 UpdTerminator; -} FSPT_UPD; - -#pragma pack(pop) - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/75630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3c11c6f68d879b944f7b4ed0fde0ee4aae204b9 Gerrit-Change-Number: 75630 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: crossgcc: Upgrade LLVM from version 16.0.4 to 16.0.5
by Felix Singer (Code Review) 04 Jun '23

04 Jun '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75635?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: crossgcc: Upgrade LLVM from version 16.0.4 to 16.0.5 ...................................................................... crossgcc: Upgrade LLVM from version 16.0.4 to 16.0.5 Change-Id: I1f227bf55bac51e6226ca5d13156e54220e33629 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75635 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/releases/coreboot-4.21-relnotes.md M util/crossgcc/buildgcc D util/crossgcc/sum/clang-16.0.4.src.tar.xz.cksum A util/crossgcc/sum/clang-16.0.5.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-16.0.4.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-16.0.5.src.tar.xz.cksum D util/crossgcc/sum/cmake-16.0.4.src.tar.xz.cksum A util/crossgcc/sum/cmake-16.0.5.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-16.0.4.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-16.0.5.src.tar.xz.cksum D util/crossgcc/sum/llvm-16.0.4.src.tar.xz.cksum A util/crossgcc/sum/llvm-16.0.5.src.tar.xz.cksum 12 files changed, 7 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/Documentation/releases/coreboot-4.21-relnotes.md b/Documentation/releases/coreboot-4.21-relnotes.md index a57b456..82e30ab 100644 --- a/Documentation/releases/coreboot-4.21-relnotes.md +++ b/Documentation/releases/coreboot-4.21-relnotes.md @@ -23,7 +23,7 @@ ### Toolchain updates * Upgrade IASL from 20221020 to 20230331 -* Upgrade LLVM from 15.0.7 to 16.0.4 +* Upgrade LLVM from 15.0.7 to 16.0.5 * Upgrade nasm from 2.15.05 to 2.16.01 * Upgrade CMake from 3.26.3 to 3.26.4 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 6447cdc..9f86995 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -41,7 +41,7 @@ BINUTILS_VERSION=2.40 IASL_VERSION=20230331 # CLANG version number -CLANG_VERSION=16.0.4 +CLANG_VERSION=16.0.5 CMAKE_VERSION=3.26.4 NASM_VERSION=2.16.01 diff --git a/util/crossgcc/sum/clang-16.0.4.src.tar.xz.cksum b/util/crossgcc/sum/clang-16.0.4.src.tar.xz.cksum deleted file mode 100644 index 2173ff6..0000000 --- a/util/crossgcc/sum/clang-16.0.4.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -32a497da79d7d19dd48e840128423f8b68c3b1b7 tarballs/clang-16.0.4.src.tar.xz diff --git a/util/crossgcc/sum/clang-16.0.5.src.tar.xz.cksum b/util/crossgcc/sum/clang-16.0.5.src.tar.xz.cksum new file mode 100644 index 0000000..04f2648 --- /dev/null +++ b/util/crossgcc/sum/clang-16.0.5.src.tar.xz.cksum @@ -0,0 +1 @@ +ad47162ae20fdd85e2db27e1a00a989c88dcacbe tarballs/clang-16.0.5.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-16.0.4.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-16.0.4.src.tar.xz.cksum deleted file mode 100644 index 40afb52..0000000 --- a/util/crossgcc/sum/clang-tools-extra-16.0.4.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -9115491127500d6913e4f042293f088f522f8aea tarballs/clang-tools-extra-16.0.4.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-16.0.5.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-16.0.5.src.tar.xz.cksum new file mode 100644 index 0000000..8e5cd8c --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-16.0.5.src.tar.xz.cksum @@ -0,0 +1 @@ +38f9ca678f40617f760b4da5795e92be0e6d573b tarballs/clang-tools-extra-16.0.5.src.tar.xz diff --git a/util/crossgcc/sum/cmake-16.0.4.src.tar.xz.cksum b/util/crossgcc/sum/cmake-16.0.4.src.tar.xz.cksum deleted file mode 100644 index cb1ae99..0000000 --- a/util/crossgcc/sum/cmake-16.0.4.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -4d042fe6ccff719da5bcf8bab977050a1f2b3c77 tarballs/cmake-16.0.4.src.tar.xz diff --git a/util/crossgcc/sum/cmake-16.0.5.src.tar.xz.cksum b/util/crossgcc/sum/cmake-16.0.5.src.tar.xz.cksum new file mode 100644 index 0000000..d78ef2d --- /dev/null +++ b/util/crossgcc/sum/cmake-16.0.5.src.tar.xz.cksum @@ -0,0 +1 @@ +3330310405697793ec3d24a63233e22713e1c808 tarballs/cmake-16.0.5.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-16.0.4.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-16.0.4.src.tar.xz.cksum deleted file mode 100644 index 58ac022..0000000 --- a/util/crossgcc/sum/compiler-rt-16.0.4.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -d19f56f8bd675f496d78c63ac4011795bc1eafe0 tarballs/compiler-rt-16.0.4.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-16.0.5.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-16.0.5.src.tar.xz.cksum new file mode 100644 index 0000000..72c7ae4 --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-16.0.5.src.tar.xz.cksum @@ -0,0 +1 @@ +6db2ebf9a345a8e42011888359de65aea37c75ba tarballs/compiler-rt-16.0.5.src.tar.xz diff --git a/util/crossgcc/sum/llvm-16.0.4.src.tar.xz.cksum b/util/crossgcc/sum/llvm-16.0.4.src.tar.xz.cksum deleted file mode 100644 index 0089f25..0000000 --- a/util/crossgcc/sum/llvm-16.0.4.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -90c3e2ba2855eae6997e4074347417b93786838d tarballs/llvm-16.0.4.src.tar.xz diff --git a/util/crossgcc/sum/llvm-16.0.5.src.tar.xz.cksum b/util/crossgcc/sum/llvm-16.0.5.src.tar.xz.cksum new file mode 100644 index 0000000..84e1e56 --- /dev/null +++ b/util/crossgcc/sum/llvm-16.0.5.src.tar.xz.cksum @@ -0,0 +1 @@ +ce2c4a55b249a3076e89c31d920f06a65510c4dc tarballs/llvm-16.0.5.src.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/75635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f227bf55bac51e6226ca5d13156e54220e33629 Gerrit-Change-Number: 75635 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[master]: crossgcc: Upgrade CMake from version 3.26.3 to 3.26.4
by Felix Singer (Code Review) 04 Jun '23

04 Jun '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75634?usp=email ) Change subject: crossgcc: Upgrade CMake from version 3.26.3 to 3.26.4 ...................................................................... crossgcc: Upgrade CMake from version 3.26.3 to 3.26.4 Change-Id: Id6dca6be8f7a82eadcbc18b4736219faf51b843c Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75634 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M Documentation/releases/coreboot-4.21-relnotes.md M util/crossgcc/buildgcc D util/crossgcc/sum/cmake-3.26.3.tar.gz.cksum A util/crossgcc/sum/cmake-3.26.4.tar.gz.cksum 4 files changed, 3 insertions(+), 2 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/Documentation/releases/coreboot-4.21-relnotes.md b/Documentation/releases/coreboot-4.21-relnotes.md index ae83539..a57b456 100644 --- a/Documentation/releases/coreboot-4.21-relnotes.md +++ b/Documentation/releases/coreboot-4.21-relnotes.md @@ -25,6 +25,7 @@ * Upgrade IASL from 20221020 to 20230331 * Upgrade LLVM from 15.0.7 to 16.0.4 * Upgrade nasm from 2.15.05 to 2.16.01 +* Upgrade CMake from 3.26.3 to 3.26.4 Additional coreboot changes --------------------------- diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index f0fb803..6447cdc 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -42,7 +42,7 @@ IASL_VERSION=20230331 # CLANG version number CLANG_VERSION=16.0.4 -CMAKE_VERSION=3.26.3 +CMAKE_VERSION=3.26.4 NASM_VERSION=2.16.01 # Filename for each package diff --git a/util/crossgcc/sum/cmake-3.26.3.tar.gz.cksum b/util/crossgcc/sum/cmake-3.26.3.tar.gz.cksum deleted file mode 100644 index cac6425..0000000 --- a/util/crossgcc/sum/cmake-3.26.3.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -03881b9004a56b5b324503f48ded62afb55a5f52 tarballs/cmake-3.26.3.tar.gz diff --git a/util/crossgcc/sum/cmake-3.26.4.tar.gz.cksum b/util/crossgcc/sum/cmake-3.26.4.tar.gz.cksum new file mode 100644 index 0000000..9b32586 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.26.4.tar.gz.cksum @@ -0,0 +1 @@ +8aedeb1dcd57f0b3c8953ac3589a898373899faa tarballs/cmake-3.26.4.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/75634?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6dca6be8f7a82eadcbc18b4736219faf51b843c Gerrit-Change-Number: 75634 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/meteorlake: Apply PCIe RP mask based on SoC type
by Subrata Banik (Code Review) 04 Jun '23

04 Jun '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75608?usp=email ) Change subject: soc/intel/meteorlake: Apply PCIe RP mask based on SoC type ...................................................................... soc/intel/meteorlake: Apply PCIe RP mask based on SoC type This patch ensures to update the FSP-M UPDs related to PCIe RP mask properly as per the SoC type. For example: PCIe RPs belong to the SoC/IOE die for MTL-U/P whereelse PCIe RPs are from PCH die in case of MTL-S. BUG=b:276697173 TEST=Able to build and boot google/rex. Change-Id: Ice81553274682476bb4c927061b1196dc142836d Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75608 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/soc/intel/meteorlake/romstage/fsp_params.c 1 file changed, 12 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 0173060..bdc4f7a 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -73,9 +73,18 @@ } /* PCIE ports */ - m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pcie_rp_table()); - pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, config->pcie_rp, - get_max_pcie_port()); + if (CONFIG(SOC_INTEL_METEORLAKE_U_P)) { + m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pcie_rp_table()); + m_cfg->PchPcieRpEnableMask = 0; /* Don't care about PCH PCIE RP Mask */ + pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, config->pcie_rp, + get_max_pcie_port()); + } else { + /* + * FIXME: Implement PCIe RP mask for `PchPcieRpEnableMask` and + * perform pcie_rp_init(). + */ + m_cfg->PcieRpEnableMask = 0; /* Don't care about SOC/IOE PCIE RP Mask */ + } } static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/75608?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice81553274682476bb4c927061b1196dc142836d Gerrit-Change-Number: 75608 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/intel/mtlrvp: Select SOC_INTEL_METEORLAKE_U_P
by Subrata Banik (Code Review) 04 Jun '23

04 Jun '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75607?usp=email ) Change subject: mb/intel/mtlrvp: Select SOC_INTEL_METEORLAKE_U_P ...................................................................... mb/intel/mtlrvp: Select SOC_INTEL_METEORLAKE_U_P Intel/MTLRVP is built with Intel Meteor Lake-U SoC, so select it. Currently, there is no functional difference, but in the future FSP UPD parameters can be overridden properly. BUG=b:276697173 TEST=Able to build and boot intel/mtlrvp. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I8b1dec47ef9d12ac50317b86c4f0bc5fbe4e4dc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75607 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/mainboard/intel/mtlrvp/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Tarun Tuli: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index de114c4..ea6c6cb 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -18,7 +18,7 @@ select HAVE_SPD_IN_CBFS select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_CSE_LITE_SKU - select SOC_INTEL_METEORLAKE + select SOC_INTEL_METEORLAKE_U_P config BOARD_INTEL_MTLRVP_P select BOARD_INTEL_MTLRVP_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/75607?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b1dec47ef9d12ac50317b86c4f0bc5fbe4e4dc3 Gerrit-Change-Number: 75607 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[master]: mb/google/rex: Select SOC_INTEL_METEORLAKE_U_P
by Subrata Banik (Code Review) 04 Jun '23

04 Jun '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75612?usp=email ) Change subject: mb/google/rex: Select SOC_INTEL_METEORLAKE_U_P ...................................................................... mb/google/rex: Select SOC_INTEL_METEORLAKE_U_P Google/Rex is built with Intel Meteor Lake-U SoC, so select it. Currently, there is no functional difference, but in the future FSP UPD parameters can be overridden properly. BUG=b:276697173 TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I4c233e0a8ce58998dc1a0379662e386f9b3d0073 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75612 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 89a2f81..cf038b7 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -38,7 +38,7 @@ select HAVE_SLP_S0_GATE select MAINBOARD_HAS_CHROMEOS select MEMORY_SOLDERDOWN - select SOC_INTEL_METEORLAKE + select SOC_INTEL_METEORLAKE_U_P select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 -- To view, visit https://review.coreboot.org/c/coreboot/+/75612?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c233e0a8ce58998dc1a0379662e386f9b3d0073 Gerrit-Change-Number: 75612 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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