coreboot-gerrit June 2023

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[M] Change in coreboot[master]: Documentation: Finalize 4.20 release notes
by Martin L Roth (Code Review) 04 Jun '23

04 Jun '23

Attention is currently required from: Angel Pons, Jason Glenesk, Martin L Roth, Nico Huber. Hello Angel Pons, Felix Singer, Jason Glenesk, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75636?usp=email to look at the new patch set (#2). Change subject: Documentation: Finalize 4.20 release notes ...................................................................... Documentation: Finalize 4.20 release notes Update the 4.20 release notes to the final post-release version. This fixes a few typos, updates the statistics to include the final few patches, and adds a note about the licensing issues which required a version bump to 4.20.1. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I350535b8aa531642e161f1cad4752452f9171647 --- M Documentation/releases/coreboot-4.20-relnotes.md 1 file changed, 41 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/75636/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75636?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I350535b8aa531642e161f1cad4752452f9171647 Gerrit-Change-Number: 75636 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/google/rex: add macro for touchscreen IRQ
by Martin L Roth (Code Review) 04 Jun '23

04 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74944?usp=email ) Change subject: mb/google/rex: add macro for touchscreen IRQ ...................................................................... mb/google/rex: add macro for touchscreen IRQ BUG=b:278783755 Signed-off-by: Eran Mitrani <mitrani(a)google.com> Change-Id: I2a6de778c7ab30a9946e100cb70c092ba98496e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74944 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h b/src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h index 35e055b..755574e 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h +++ b/src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h @@ -22,5 +22,7 @@ #define GPIO_MEM_CONFIG_2 GPP_E01 #define GPIO_MEM_CONFIG_3 GPP_E12 #define GPIO_MEM_CH_SEL GPP_E13 +/* Touchscreen IRQ */ +#define TOUCH_SCR_IRQ GPP_C07_IRQ #endif /* __BASEBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74944?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a6de778c7ab30a9946e100cb70c092ba98496e3 Gerrit-Change-Number: 74944 Gerrit-PatchSet: 8 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/sifive: Comment out set but unused variables
by Martin L Roth (Code Review) 04 Jun '23

04 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75356?usp=email ) Change subject: soc/sifive: Comment out set but unused variables ...................................................................... soc/sifive: Comment out set but unused variables The code is supposed to output debug messages but is commented out, so do the same for variables. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ief1f9d2175fe1375fe6ac4bb0765b00513321fa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75356 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/sifive/fu540/ux00ddr.h 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: Angel Pons: Looks good to me, but someone else must approve build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/soc/sifive/fu540/ux00ddr.h b/src/soc/sifive/fu540/ux00ddr.h index bf856f3..d468a8e 100644 --- a/src/soc/sifive/fu540/ux00ddr.h +++ b/src/soc/sifive/fu540/ux00ddr.h @@ -148,9 +148,9 @@ size_t ddrphyreg = ahbregaddr + 0x2000; - uint64_t fails=0; + // uint64_t fails=0; uint32_t slicebase = 0; - uint32_t dq = 0; + // uint32_t dq = 0; // check errata condition for (uint32_t slice = 0; slice < 8; slice++) { @@ -175,7 +175,7 @@ // print error message on failure if (failc0 || failc1) { //if (fails==0) uart_puts((void*) UART0_CTRL_ADDR, "DDR error in fixing up \n"); - fails |= (1<<dq); + //fails |= (1<<dq); /* char slicelsc = '0'; */ /* char slicemsc = '0'; */ /* slicelsc += (dq % 10); */ @@ -187,7 +187,7 @@ //else uart_puts((void*) UART0_CTRL_ADDR, "D"); //uart_puts((void*) UART0_CTRL_ADDR, "\n"); } - dq++; + //dq++; } } slicebase+=128; -- To view, visit https://review.coreboot.org/c/coreboot/+/75356?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief1f9d2175fe1375fe6ac4bb0765b00513321fa6 Gerrit-Change-Number: 75356 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: cpu/x86/smm: Drop fxsave/fxrstor logic
by Martin L Roth (Code Review) 04 Jun '23

04 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75317?usp=email ) Change subject: cpu/x86/smm: Drop fxsave/fxrstor logic ...................................................................... cpu/x86/smm: Drop fxsave/fxrstor logic Since we now explicitly compile both ramstage and smihandler code without floating point operations and associated registers we don't need to save/restore floating point registers. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I180b9781bf5849111501ae8e9806554a7851c0da Reviewed-on: https://review.coreboot.org/c/coreboot/+/75317 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/cpu/x86/smm/smm_module_loader.c M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/smm.h 3 files changed, 15 insertions(+), 74 deletions(-) Approvals: Elyes Haouas: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 47a2831..f827e7b 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -13,13 +13,7 @@ #include <string.h> #include <types.h> -#define FXSAVE_SIZE 512 #define SMM_CODE_SEGMENT_SIZE 0x10000 -/* FXSAVE area during relocation. While it may not be strictly needed the - SMM stub code relies on the FXSAVE area being non-zero to enable SSE - instructions within SMM mode. */ -static uint8_t fxsave_area_relocation[CONFIG_MAX_CPUS][FXSAVE_SIZE] -__attribute__((aligned(16))); /* * Components that make up the SMRAM: @@ -56,7 +50,7 @@ * developer's manuals (volume 3, chapter 34). SMRAM is divided up into the * following regions: * +-----------------+ Top of SMRAM - * | | <- MSEG, FXSAVE + * | MSEG | * +-----------------+ * | common | * | smi handler | 64K @@ -240,8 +234,7 @@ * by the permanent handler can be used during relocation. */ static int smm_module_setup_stub(const uintptr_t smbase, const size_t smm_size, - struct smm_loader_params *params, - void *const fxsave_area) + struct smm_loader_params *params) { struct rmodule smm_stub; if (rmodule_parse(&_binary_smmstub_start, &smm_stub)) { @@ -266,8 +259,6 @@ stub_params->stack_top = stack_top; stub_params->stack_size = g_stack_size; stub_params->c_handler = (uintptr_t)params->handler; - stub_params->fxsave_area = (uintptr_t)fxsave_area; - stub_params->fxsave_area_size = FXSAVE_SIZE; /* This runs on the BSP. All the APs are its siblings */ struct cpu_info *info = cpu_info(); @@ -322,8 +313,7 @@ params->num_cpus = CONFIG_MAX_CPUS; printk(BIOS_SPEW, "%s: exit\n", __func__); - return smm_module_setup_stub(smram, SMM_DEFAULT_SIZE, - params, fxsave_area_relocation); + return smm_module_setup_stub(smram, SMM_DEFAULT_SIZE, params); } static void setup_smihandler_params(struct smm_runtime *mod_params, @@ -363,8 +353,8 @@ region_end(&region)); } -/* STM + FX_SAVE + Handler + (Stub + Save state) * CONFIG_MAX_CPUS + stacks */ -#define SMM_REGIONS_ARRAY_SIZE (1 + 1 + 1 + CONFIG_MAX_CPUS * 2 + 1) +/* STM + Handler + (Stub + Save state) * CONFIG_MAX_CPUS + stacks */ +#define SMM_REGIONS_ARRAY_SIZE (1 + 1 + CONFIG_MAX_CPUS * 2 + 1) static int append_and_check_region(const struct region smram, const struct region region, @@ -406,8 +396,6 @@ * | BIOS resource | * | list (STM) | * +-----------------+ - * | fxsave area | - * +-----------------+ * | smi handler | * | ... | * +-----------------+ <- cpu0 @@ -453,19 +441,10 @@ printk(BIOS_DEBUG, "BIOS res list 0x%x\n", CONFIG_BIOS_RESOURCE_LIST_SIZE); } - const size_t fx_save_area_size = CONFIG(SSE) ? FXSAVE_SIZE * params->num_cpus : 0; - struct region fx_save = {}; - if (CONFIG(SSE)) { - fx_save.offset = smram_top - stm_size - fx_save_area_size; - fx_save.size = fx_save_area_size; - if (append_and_check_region(smram, fx_save, region_list, "FX_SAVE")) - return -1; - } - const size_t handler_size = rmodule_memory_size(&smi_handler); const size_t handler_alignment = rmodule_load_alignment(&smi_handler); const uintptr_t handler_base = - ALIGN_DOWN(smram_top - stm_size - fx_save_area_size - handler_size, + ALIGN_DOWN(smram_top - stm_size - handler_size, handler_alignment); struct region handler = { .offset = handler_base, @@ -506,6 +485,5 @@ params->handler = rmodule_entry(&smi_handler); setup_smihandler_params(smihandler_params, smram_base, smram_size, params); - return smm_module_setup_stub(stub_segment_base, smram_size, params, - (void *)region_offset(&fx_save)); + return smm_module_setup_stub(stub_segment_base, smram_size, params); } diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index e44e99d..673ab2c 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -22,10 +22,6 @@ .long 0 c_handler: .long 0 -fxsave_area: -.long 0 -fxsave_area_size: -.long 0 /* apic_to_cpu_num is a table mapping the default APIC id to CPU num. If the * APIC id is found at the given index, the contiguous CPU number is index * into the table. */ @@ -171,9 +167,7 @@ * not be assigned. Use the fallback stack and check this condition in * C handler. */ movl $(fallback_stack_top), %esp - /* Clear fxsave location as there will be no saving/restoring. */ - xor %edi, %edi - jmp 2f + jmp align_stack 1: movl stack_size, %eax mul %ecx /* %eax(stack_size) * %ecx(cpu) = %eax(offset) */ @@ -193,32 +187,10 @@ pushl $0x0 mov %esp, %ebp - /* Allocate locals (fxsave, efer_backup) */ - subl $0xc, %esp + /* Allocate locals (efer_backup) */ + subl $0x8, %esp - /* calculate fxsave location */ - mov fxsave_area, %edi - test %edi, %edi - jz 2f - movl fxsave_area_size, %eax - mul %ecx - add %eax, %edi - -2: - /* Save location of fxsave area. */ - mov %edi, -4(%ebp) - test %edi, %edi - jz 1f - - /* Enable sse instructions. */ - mov %cr4, %eax - orl $(CR4_OSFXSR | CR4_OSXMMEXCPT), %eax - mov %eax, %cr4 - - /* Save FP state. */ - fxsave (%edi) - -1: +align_stack: /* Align stack to 16 bytes. Another 32 bytes are pushed below. */ andl $0xfffffff0, %esp @@ -227,8 +199,8 @@ /* Backup IA32_EFER. Preserves ebx. */ movl $(IA32_EFER), %ecx rdmsr - movl %eax, -0x8(%ebp) - movl %edx, -0xc(%ebp) + movl %eax, -0x4(%ebp) + movl %edx, -0x8(%ebp) /* entry64.inc preserves ebx, esi, edi, ebp */ #include <cpu/x86/64bit/entry64.inc> @@ -262,8 +234,8 @@ /* Restore IA32_EFER as RSM doesn't restore MSRs. */ movl $(IA32_EFER), %ecx rdmsr - movl -0x8(%ebp), %eax - movl -0xc(%ebp), %edx + movl -0x4(%ebp), %eax + movl -0x8(%ebp), %edx wrmsr @@ -275,13 +247,6 @@ mov c_handler, %eax call *%eax #endif - /* Retrieve fxsave location. */ - mov -4(%ebp), %edi - test %edi, %edi - jz 1f - - /* Restore FP state. */ - fxrstor (%edi) 1: /* Exit from SM mode. */ diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 4c97f21..68c7c3b 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -98,8 +98,6 @@ u32 stack_size; u32 stack_top; u32 c_handler; - u32 fxsave_area; - u32 fxsave_area_size; /* The apic_id_to_cpu provides a mapping from APIC id to CPU number. * The CPU number is indicated by the index into the array by matching * the default APIC id and value at the index. The stub loader -- To view, visit https://review.coreboot.org/c/coreboot/+/75317?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I180b9781bf5849111501ae8e9806554a7851c0da Gerrit-Change-Number: 75317 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util/qemu: Revise q35 configs
by Martin L Roth (Code Review) 04 Jun '23

04 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67026?usp=email ) Change subject: util/qemu: Revise q35 configs ...................................................................... util/qemu: Revise q35 configs Add an NVMe drive and be more conservative with hotplug-capable PCIe ports. QEMU treats everything as hotpluggable by default, so devices can be added at runtime. However, this leads to unrealistic resource allocations with PCIEXP_HOTPLUG enabled. Tested recent allocator changes with QEMU/Q35 config and: $ make qemu QEMU_EXTRA_CFGS=util/qemu/q35-alpine.cfg Change-Id: I23746b642329356c6767b04ec177cd9411e3adb9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67026 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M util/qemu/q35-alpine.cfg M util/qemu/q35-base.cfg 2 files changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved diff --git a/util/qemu/q35-alpine.cfg b/util/qemu/q35-alpine.cfg index bcbde97..513f4d7 100644 --- a/util/qemu/q35-alpine.cfg +++ b/util/qemu/q35-alpine.cfg @@ -9,6 +9,7 @@ bus = "alpine-root" addr = "00.0" chassis = "10" + hotplug = "off" [device "alpine-nhi"] driver = "pci-testdev" @@ -21,6 +22,7 @@ bus = "alpine-root" addr = "01.0" chassis = "11" + hotplug = "off" [device "alpine-up"] driver = "x3130-upstream" @@ -48,6 +50,7 @@ bus = "alpine-up" addr = "04.0" chassis = "24" + hotplug = "off" [device "alpine-xhci"] driver = "nec-usb-xhci" @@ -59,3 +62,4 @@ bus = "alpine-root" addr = "02.0" chassis = "12" + hotplug = "off" diff --git a/util/qemu/q35-base.cfg b/util/qemu/q35-base.cfg index 87dcfcd..53eef47 100644 --- a/util/qemu/q35-base.cfg +++ b/util/qemu/q35-base.cfg @@ -18,7 +18,13 @@ driver = "pcie-root-port" bus = "pcie.0" addr = "01.0" + hotplug = "off" +[device "ssd"] + driver = "nvme" + bus = "q35-peg" + addr = "00.0" + serial = "0" [device "q35-igpu"] driver = "VGA" @@ -85,6 +91,7 @@ addr = "1c.0" port = "1" chassis = "1" + hotplug = "off" [device "ich9-pcie-port-2"] driver = "ioh3420" @@ -93,6 +100,7 @@ addr = "1c.1" port = "2" chassis = "2" + hotplug = "off" [device "ich9-pcie-port-3"] driver = "ioh3420" @@ -101,6 +109,7 @@ addr = "1c.2" port = "3" chassis = "3" + hotplug = "off" [device "ich9-pcie-port-4"] driver = "ioh3420" @@ -109,6 +118,7 @@ addr = "1c.3" port = "4" chassis = "4" + hotplug = "off" [device "ich9-pcie-port-5"] driver = "ioh3420" -- To view, visit https://review.coreboot.org/c/coreboot/+/67026?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23746b642329356c6767b04ec177cd9411e3adb9 Gerrit-Change-Number: 67026 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/mendocino: Print content of manifest file
by Martin L Roth (Code Review) 04 Jun '23

04 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Grzegorz Bernacki, Jakub Czapiga, Jason Glenesk, Matt DeVillier, Paul Menzel, Raul Rangel. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74269?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/amd/mendocino: Print content of manifest file ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > this will only return the correct values if the amdfw part wasn't replaced after the build. […] Marking unresolved so this doesn't get merged without being noticed. Grzegorz, update the release notes or not as you choose, then mark this as fixed. It can me merged immediately after that, so long as the release notes are the only change. -- To view, visit https://review.coreboot.org/c/coreboot/+/74269?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8df54b74cd987b4a3be635932d38ea178d0b0311 Gerrit-Change-Number: 74269 Gerrit-PatchSet: 8 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 04 Jun 2023 19:20:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/brya/var/taeko: Fix PLD group order
by Martin L Roth (Code Review) 04 Jun '23

04 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75572?usp=email ) Change subject: mb/google/brya/var/taeko: Fix PLD group order ...................................................................... mb/google/brya/var/taeko: Fix PLD group order Ensure USB-C ports' _PLD group numbers appear in order. get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group token to match with the Type-C port number. BUG=b:216490477 TEST=build coreboot and system boot into OS. BRANCH=firmware-brya-14505.B Change-Id: I5c0395d33ee47ab1c7d45f33d6afb063b8263836 Signed-off-by: Won Chung <wonchung(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75572 Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/taeko/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Tarun Tuli: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 54a5ba7..de188e1 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -599,7 +599,7 @@ register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" register "usb_lpm_incapable" = "true" device ref tcss_usb3_port3 on probe DB_USB DB_USB3_NO_A @@ -623,7 +623,7 @@ register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on probe DB_USB DB_USB3_NO_A probe DB_USB DB_USB3_1C_1A -- To view, visit https://review.coreboot.org/c/coreboot/+/75572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c0395d33ee47ab1c7d45f33d6afb063b8263836 Gerrit-Change-Number: 75572 Gerrit-PatchSet: 3 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/google/brya/var/marasov: Fix PLD group order
by Martin L Roth (Code Review) 04 Jun '23

04 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75571?usp=email ) Change subject: mb/google/brya/var/marasov: Fix PLD group order ...................................................................... mb/google/brya/var/marasov: Fix PLD group order Ensure USB-C ports' _PLD group numbers appear in order. get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group token to match with the Type-C port number. BUG=b:216490477 TEST=build coreboot and system boot into OS. BRANCH=firmware-brya-14505.B Change-Id: I51ff0991565d60807c100b33fb66ab10cc48b8e1 Signed-off-by: Won Chung <wonchung(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75571 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/mainboard/google/brya/variants/marasov/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tarun Tuli: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index dfbf3f6..581eb3b 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -372,7 +372,7 @@ register "desc" = ""USB3 Type-C Port C2 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" register "usb_lpm_incapable" = "true" device ref tcss_usb3_port3 on end end @@ -393,7 +393,7 @@ register "desc" = ""USB2 Type-C Port C2 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/75571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51ff0991565d60807c100b33fb66ab10cc48b8e1 Gerrit-Change-Number: 75571 Gerrit-PatchSet: 3 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/google/brya/var/constitution: Fix PLD group order
by Martin L Roth (Code Review) 04 Jun '23

04 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75570?usp=email ) Change subject: mb/google/brya/var/constitution: Fix PLD group order ...................................................................... mb/google/brya/var/constitution: Fix PLD group order Ensure USB-C ports' _PLD group numbers appear in order. get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group token to match with the Type-C port number. BUG=b:216490477 TEST=build coreboot and system boot into OS. BRANCH=firmware-brya-14505.B Change-Id: Ib564ffe272e73f46ec6608420dc431c8b017fb65 Signed-off-by: Won Chung <wonchung(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75570 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/mainboard/google/brya/variants/constitution/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: Tarun Tuli: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/constitution/overridetree.cb b/src/mainboard/google/brya/variants/constitution/overridetree.cb index 4b894b0..17965fd 100644 --- a/src/mainboard/google/brya/variants/constitution/overridetree.cb +++ b/src/mainboard/google/brya/variants/constitution/overridetree.cb @@ -244,14 +244,14 @@ register "desc" = ""USB3 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port2 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(1, 3))" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(3, 1))" device ref tcss_usb3_port3 on end end end @@ -271,14 +271,14 @@ register "desc" = ""USB2 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(1, 3))" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/75570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib564ffe272e73f46ec6608420dc431c8b017fb65 Gerrit-Change-Number: 75570 Gerrit-PatchSet: 3 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/google/brya/var/kuldax: use RPL FSP headers
by Martin L Roth (Code Review) 04 Jun '23

04 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75599?usp=email ) Change subject: mb/google/brya/var/kuldax: use RPL FSP headers ...................................................................... mb/google/brya/var/kuldax: use RPL FSP headers Select SOC_INTEL_RAPTORLAKE for kuldax so that it will use the RPL FSP headers for kuldax. BUG=b:285406822 BRANCH=firmware-brya-14505.B TEST="FW_NAME=kuldax emerge-brask coreboot-private-files-baseboard-brya coreboot chromeos-bootimage" Cq-Depend: chromium:4583807, chrome-internal:6003096 Change-Id: Icbf8b26bc2bfee2559cce236bde80a99f8bff859 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75599 Reviewed-by: Bob Moragues <moragues(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Derek Huang <derekhuang(a)google.com> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Bob Moragues: Looks good to me, but someone else must approve build bot (Jenkins): Verified Derek Huang: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 6108067..44c1156 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -262,6 +262,7 @@ select BOARD_GOOGLE_BASEBOARD_BRASK select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GENESYSLOGIC_GL9755 + select SOC_INTEL_RAPTORLAKE config BOARD_GOOGLE_JOXER bool "-> Joxer" -- To view, visit https://review.coreboot.org/c/coreboot/+/75599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbf8b26bc2bfee2559cce236bde80a99f8bff859 Gerrit-Change-Number: 75599 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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