coreboot-gerrit June 2023

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[M] Change in coreboot[master]: soc/amd/phoenix: Update USB device alias
by Felix Held (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Eric Lai, Fred Reitberger, Jason Glenesk, Jon Murphy, Karthik Ramasubramanian, Martin L Roth, Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75615?usp=email ) Change subject: soc/amd/phoenix: Update USB device alias ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: hmm, this is some odd numbering; missed that the last two xhci controllers have the first usb ports -- To view, visit https://review.coreboot.org/c/coreboot/+/75615?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1058279fe5b0e3131608a0b9bbd708dbbde7e87 Gerrit-Change-Number: 75615 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 05 Jun 2023 14:47:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Use memcpy library function
by Nico Huber (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Sridhar Siricilla. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75620?usp=email ) Change subject: soc/intel/common: Use memcpy library function ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: If I found the right types, `hotfix` and `build` are swapped. -- To view, visit https://review.coreboot.org/c/coreboot/+/75620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff6c9a663e9e3f80cf3fb2f6d6203a95c3fea20c Gerrit-Change-Number: 75620 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Mon, 05 Jun 2023 14:33:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/stoneyridge/northbridge: reserve PCI config IO ports
by Nico Huber (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Felix Held, Matt DeVillier. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75619?usp=email ) Change subject: soc/amd/stoneyridge/northbridge: reserve PCI config IO ports ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75619?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I014ffe3ee94ec153e91113f9a17e89f24ca040b3 Gerrit-Change-Number: 75619 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Jun 2023 14:27:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/*/root_complex: reserve PCI config IO ports
by Nico Huber (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Eric Lai, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75556?usp=email ) Change subject: soc/amd/*/root_complex: reserve PCI config IO ports ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie42260902ee2b383dd5867ac813cae029f706f2d Gerrit-Change-Number: 75556 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Jun 2023 14:27:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/x86/include/arch/vga: add defines for VGA MMIO addresses
by Nico Huber (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75618?usp=email ) Change subject: arch/x86/include/arch/vga: add defines for VGA MMIO addresses ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4a4f39a4e876bbba59620d689cd56c3c286daae Gerrit-Change-Number: 75618 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Jun 2023 14:24:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: arch/arm64: Add EL1/EL2/EL3 support for arm64
by Nico Huber (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Milosevic, Julius Werner, Lean Sheng Tan, Maximilian Brune. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74798?usp=email ) Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64 ...................................................................... Patch Set 5: (1 comment) File src/arch/arm64/transition_asm.S: https://review.coreboot.org/c/coreboot/+/74798/comment/cd3d83c4_eda4b896 : PS5, Line 155: mrs x1, currentel > I know its like this in most of our code, but personally I don't understand why I would want to pref […] We prefer linker garbage-collection over preprocessing where possible. It helps to keep the code readable. Sometimes it may seem like overkill, but in the past, code got really messy due to #if. Also, it allows us to build test more code at once. That's for C, in `.S` things are different ofc. -- To view, visit https://review.coreboot.org/c/coreboot/+/74798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e Gerrit-Change-Number: 74798 Gerrit-PatchSet: 5 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Mon, 05 Jun 2023 14:20:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Use memcpy library function
by Sridhar Siricilla (Code Review) 05 Jun '23

05 Jun '23

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75620?usp=email ) Change subject: soc/intel/common: Use memcpy library function ...................................................................... soc/intel/common: Use memcpy library function The patch uses memcpy library function instead of copying the field by field of same structure variables. TEST=Build the code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Iff6c9a663e9e3f80cf3fb2f6d6203a95c3fea20c --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 2 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/75620/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 733f68b..0db919c 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -934,11 +934,7 @@ return CB_ERR; } - fw_ver->major = man_hdr.binary_version.major; - fw_ver->minor = man_hdr.binary_version.minor; - fw_ver->hotfix = man_hdr.binary_version.hotfix; - fw_ver->build = man_hdr.binary_version.build; - + memcpy(fw_ver, &man_hdr.binary_version, sizeof(struct fw_version)); return CB_SUCCESS; } @@ -950,11 +946,7 @@ subpart_entry = (struct subpart_entry *)(ptr + SUBPART_HEADER_SZ); man_hdr = (struct subpart_entry_manifest_header *)(ptr + subpart_entry->offset_bytes); - - fw_ver->major = man_hdr->binary_version.major; - fw_ver->minor = man_hdr->binary_version.minor; - fw_ver->hotfix = man_hdr->binary_version.hotfix; - fw_ver->build = man_hdr->binary_version.build; + memcpy(fw_ver, &man_hdr->binary_version, sizeof(struct fw_version)); } static enum cb_err cse_prep_for_component_update(const struct cse_bp_info *cse_bp_info) -- To view, visit https://review.coreboot.org/c/coreboot/+/75620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff6c9a663e9e3f80cf3fb2f6d6203a95c3fea20c Gerrit-Change-Number: 75620 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: mb/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC
by Felix Singer (Code Review) 05 Jun '23

05 Jun '23

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[S] Change in coreboot[master]: soc/amd/mendocino: Print content of manifest file
by Martin L Roth (Code Review) 05 Jun '23

05 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74269?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/mendocino: Print content of manifest file ...................................................................... soc/amd/mendocino: Print content of manifest file This adds printing content of 'manifest' file at ramstage. It allows to learn about blobs version used to build the coreboot binary, which is useful when investigating bugs. Version data are stored in CBFS file, which was generated during coreboot build. If AMD FW blobs will be manually replaced in coreboot image, versions from CBFS file are no longer valid. Log: AMDFW blobs version: type: 0x01 ver:00.3c.01.18 type: 0x08 ver:00.5a.28.00 type: 0x30 ver:2b.25.b0.10 type: 0x73 ver:00.3c.01.18 BUG=b:224780134 TEST=Tested on Skyrim device Change-Id: I8df54b74cd987b4a3be635932d38ea178d0b0311 Signed-off-by: Grzegorz Bernacki <bernacki(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74269 Reviewed-by: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/mendocino/Makefile.inc A src/soc/amd/mendocino/manifest.c 2 files changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Himanshu Sahdev: Looks good to me, but someone else must approve Eric Lai: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 8e33cf5..ac7ec6d 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -31,6 +31,7 @@ ramstage-y += mca.c ramstage-y += root_complex.c ramstage-y += xhci.c +ramstage-y += manifest.c smm-y += gpio.c smm-y += smihandler.c diff --git a/src/soc/amd/mendocino/manifest.c b/src/soc/amd/mendocino/manifest.c new file mode 100644 index 0000000..3dd9b6a --- /dev/null +++ b/src/soc/amd/mendocino/manifest.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <cbfs.h> + +static void print_blob_version(void *arg) +{ + char *version; + size_t size; + + version = cbfs_map("amdfw_manifest", &size); + + if (!version) { + printk(BIOS_WARNING, "Failed to get amdfw_manifest\n"); + return; + } + + printk(BIOS_INFO, "AMDFW blobs version:\n"); + printk(BIOS_INFO, "%.*s", (int)size, version); + + cbfs_unmap(version); +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, print_blob_version, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/74269?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8df54b74cd987b4a3be635932d38ea178d0b0311 Gerrit-Change-Number: 74269 Gerrit-PatchSet: 10 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: mb/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC
by Felix Singer (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Angel Pons, Lean Sheng Tan, Maximilian Brune, Paul Menzel, Tim Wawrzynczak. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66545?usp=email ) Change subject: mb/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC ...................................................................... Patch Set 21: (3 comments) File src/mainboard/intel/adlrvp/variants/adlrvp_s_ddr5_udimm_1dpc/overridetree.cb: https://review.coreboot.org/c/coreboot/+/66545/comment/4689e31d_715508ad : PS21, Line 3: # Configure overcurrent for USB Ports : register "usb2_ports[6]" = "USB2_PORT_MID(OC7)" # USB3/2 Type A port7 : register "usb2_ports[9]" = "USB2_PORT_MID(OC7)" # USB3/2 Type A port10 : register "usb2_ports[10]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port11 : register "usb2_ports[12]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port13 Move these to XHCI controller in devicetree https://review.coreboot.org/c/coreboot/+/66545/comment/dd7abdca_757b63fe : PS21, Line 9: #TODO check in 723858 if they are similar for all ADLRVP-S boards : # DDI_PORT_A: Combo PHY A # ADL-S RVP UDIMM 1DPC eDP1.4 Connector : # DDI_PORT_1: Combo PHY B # ADL-S RVP UDIMM 1DPC HDMI 1.4b CRLS : # DDI_PORT_2: Combo PHY C # ADL-S RVP UDIMM 1DPC DP1.4a Connector : # DDI_PORT_3: Combo PHY D # ADL-S RVP UDIMM 1DPC HDMI 2.0b ALS : # DDI_PORT_4: Combo PHY E # ADL-S RVP UDIMM 1DPC DP1.4a Connector : # Enable eDP in PortA #TODO test : #register "ddi_portA_config" = "1" : #[DDI_PORT_A] = DDI_ENABLE_HPD : register "ddi_ports_config" = "{ : [DDI_PORT_1] = DDI_ENABLE_HPD, : [DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, : [DDI_PORT_3] = DDI_ENABLE_HPD, : [DDI_PORT_4] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, : }" Move to iGPU controller in devicetree https://review.coreboot.org/c/coreboot/+/66545/comment/d9e2ab07_2d89e266 : PS21, Line 25: register "sata_salp_support" = "1" : register "sata_ports_enable" = "{ : [4] = 1, : [5] = 1, : [6] = 1, : [7] = 1, : }" : : register "sata_ports_dev_slp" = "{ : [4] = 0, : [5] = 0, : [6] = 1, : [7] = 1, : }" Move to SATA controller in devicetree -- To view, visit https://review.coreboot.org/c/coreboot/+/66545?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1f62d6dd0b00d26f8c8a71b624ba5fba4c63774 Gerrit-Change-Number: 66545 Gerrit-PatchSet: 21 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 05 Jun 2023 13:45:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit June 2023