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Change subject: soc/amd/mendocino: Print content of manifest file
......................................................................
Patch Set 9:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74269/comment/0eab7b60_11d7b63b :
PS8, Line 14: TEST=Tested on Skyrim device
> Could you post snap log here?
Done
Patchset:
PS8:
> Marking unresolved so this doesn't get merged without being noticed. […]
Done
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Hello Felix Held, Fred Reitberger, Himanshu Sahdev, Jakub Czapiga, Jason Glenesk, Karthik Ramasubramanian, Matt DeVillier, Raul Rangel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/mendocino: Print content of manifest file
......................................................................
soc/amd/mendocino: Print content of manifest file
This adds printing content of 'manifest' file at ramstage.
It allows to learn about blobs version used to build the coreboot
binary, which is useful when investigating bugs.
Version data are stored in CBFS file, which was generated during
coreboot build. If AMD FW blobs will be manually replaced in coreboot
image, versions from CBFS file are no longer valid.
Log:
AMDFW blobs version:
type: 0x01 ver:00.3c.01.18
type: 0x08 ver:00.5a.28.00
type: 0x30 ver:2b.25.b0.10
type: 0x73 ver:00.3c.01.18
BUG=b:224780134
TEST=Tested on Skyrim device
Change-Id: I8df54b74cd987b4a3be635932d38ea178d0b0311
Signed-off-by: Grzegorz Bernacki <bernacki(a)google.com>
---
M src/soc/amd/mendocino/Makefile.inc
A src/soc/amd/mendocino/manifest.c
2 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/74269/9
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Change subject: mb/google/geralt: Fix MIPI panel power on/off sequence
......................................................................
Patch Set 4: Code-Review+2
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Change subject: vboot: Drop argument to select slot from `vb2ex_ec_protect()`
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75521/comment/7c14798a_f7e5c5b6 :
PS5, Line 23: w/o this patch
with this patch?
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Hello Angel Pons, Lean Sheng Tan, Tim Wawrzynczak, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
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Change subject: mb/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC
......................................................................
mb/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC
Tested:
- Boot SeaBIOS (46de2eecf) -> Linux 6.0.1
- Boot 9elements/EDK2 (4f58f36b8) -> Linux 6.0.1, Windows 10
- M.2 SSD Slot 1: PCH SSD
- M.2 SSD Slot 2: PCH SSD
- M.2 SSD Slot 3: PCH SSD, Backside
- SATA Cable Port 1-3
- SATA Direct Connect Port
- DisplayPort Port 1,2
- HDMI Port 1,2
- PCIE x4 Slot 1
- PCIE x4 Slot 3
- USB Ports 1-4 (Backpanel)
- M.2. CNVI: WiFi (Linux 6.0.1 works, Win 10 does not)
- S3 (suspend to ram) (Linux 6.0.1 works, Win 10 does not)
- S4 (hibernate)
- M.2. CNVI: Bluetooth
- LAN GBE
missing:
- Displayport over USB-C
- some USB Ports still missing
- PCIE x4 Slot 2 (for some reason it doesn't work)
- M.2 SSD Slot 4: CPU SSD
- PEG (PCIE x16 Slot) connected to CPU
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: Ic1f62d6dd0b00d26f8c8a71b624ba5fba4c63774
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/Kconfig.name
M src/mainboard/intel/adlrvp/Makefile.inc
A src/mainboard/intel/adlrvp/devicetree_s.cb
A src/mainboard/intel/adlrvp/early_gpio_s.c
A src/mainboard/intel/adlrvp/gpio_s.c
M src/mainboard/intel/adlrvp/include/baseboard/variants.h
M src/mainboard/intel/adlrvp/memory.c
M src/mainboard/intel/adlrvp/ramstage.c
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
A src/mainboard/intel/adlrvp/variants/adlrvp_s_ddr5_udimm_1dpc/overridetree.cb
11 files changed, 578 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/66545/21
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Change subject: soc/intel/meteorlake: Fill PCI SSID parameters
......................................................................
Patch Set 7: Code-Review+2
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Change subject: vboot: Drop argument to select slot from `vb2ex_ec_protect()`
......................................................................
Patch Set 5:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75521/comment/5727f6f2_12fe9b3a :
PS4, Line 9: has
> have
Acknowledged
https://review.coreboot.org/c/coreboot/+/75521/comment/dd429af8_e65ab2d3 :
PS4, Line 11: is
> ~~is~~
Acknowledged
https://review.coreboot.org/c/coreboot/+/75521/comment/a6bd8737_46030ae6 :
PS4, Line 11: currently takes
: about 17 ms to lock down the EC.
> better to mention time savings with vboot changes instead/alongwith
Acknowledged
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Hello Harsha B R, Himanshu Sahdev, Julius Werner, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: vboot: Drop argument to select slot from `vb2ex_ec_protect()`
......................................................................
vboot: Drop argument to select slot from `vb2ex_ec_protect()`
vboot code changes have eliminated the redundant call to WP the EC-RO
region as protecting RW flash implies protecting both RO and RW flash,
so the call to protect RO is redundant. google/rex currently takes
about 17 ms to lock down the EC.
Along with vboot changes, this patch drops argument to choose between
RO and RW slot to protect while calling into `vb2ex_ec_protect()`.
It ensures vb2ex_ec_protect() is explicitly meant for protecting RW
regions.
w/o this patch:
517:waiting for EC to allow higher power draw 846,196 (17,297)
w/o this patch:
517:waiting for EC to allow higher power draw 838,258 (9,719)
Additionally, update vboot submodule to upstream main to avoid the
compilation error.
Updating from commit id 35f50c3154e5:
Fix build error when compiling without -DNDEBUG
to commit id 034907b279c9db:
vboot_reference: eliminate redundant call to write protect EC-RO
Change-Id: I2974f0cb43ba800c2aaeac4876ebaa052b5ee793
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M 3rdparty/vboot
M src/security/vboot/ec_sync.c
2 files changed, 5 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/75521/5
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