coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

1 participants
5387 discussions

[L] Change in coreboot[master]: mb/google/rex: Create ovis variant
by Jakub Czapiga (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Jakub Czapiga, Jan Dabros, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun Tuli. Hello Kapil Porwal, Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75385?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/google/rex: Create ovis variant ...................................................................... mb/google/rex: Create ovis variant BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a ; Make sure GOOGLE_OVIS built successfully Change-Id: I5c8f290cfdcb4d47c0e5e9d72c1e34073b957681 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/Kconfig.name A src/mainboard/google/rex/variants/baseboard/ovis/Makefile.inc A src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb A src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/ec.h A src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/gpio.h A src/mainboard/google/rex/variants/baseboard/ovis/memory.c A src/mainboard/google/rex/variants/ovis/Makefile.inc A src/mainboard/google/rex/variants/ovis/gpio.c A src/mainboard/google/rex/variants/ovis/include/variant/ec.h A src/mainboard/google/rex/variants/ovis/include/variant/gpio.h A src/mainboard/google/rex/variants/ovis/memory/Makefile.inc A src/mainboard/google/rex/variants/ovis/memory/dram_id.generated.txt A src/mainboard/google/rex/variants/ovis/memory/mem_parts_used.txt A src/mainboard/google/rex/variants/ovis/overridetree.cb 15 files changed, 349 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/75385/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/75385?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c8f290cfdcb4d47c0e5e9d72c1e34073b957681 Gerrit-Change-Number: 75385 Gerrit-PatchSet: 8 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Dabros <dabros(a)google.com> Gerrit-CC: Jan Dabros <jsd(a)semihalf.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jan Dabros <dabros(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7
by Harsha B R (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Dtrain Hsu, Shou-Chieh Hsu, Subrata Banik, Tarun Tuli. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75644?usp=email ) Change subject: mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8a2c0f5530c7a056e8d706c651cac1d49b2091c Gerrit-Change-Number: 75644 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Mon, 05 Jun 2023 09:27:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7
by Dtrain Hsu (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Harsha B R, Shou-Chieh Hsu, Subrata Banik, Tarun Tuli. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75644?usp=email ) Change subject: mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7 ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > If you have any test done already (as mentioned in the bug:283735051), that can be added as part of […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8a2c0f5530c7a056e8d706c651cac1d49b2091c Gerrit-Change-Number: 75644 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Mon, 05 Jun 2023 09:25:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Harsha B R <harsha.b.r(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7
by Dtrain Hsu (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Shou-Chieh Hsu, Subrata Banik, Tarun Tuli. Hello Derek Huang, Harsha B R, Shou-Chieh Hsu, Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75644?usp=email to look at the new patch set (#3). Change subject: mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7 ...................................................................... mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7 Uldren does not have PCIE device and should disable PCIE RP7 and GPP_D7 for preventing PCIe controller not power gate in S0ix. BUG=b:283735051 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage 1. PCIE RP7: cbmem -c | grep 'PCI: 00:1c.6' [SPEW ] PCI: 00:1c.6: enabled 0 [SPEW ] PCI: 00:1c.6: enabled 0 2. GPP_D7: iotools mmio_read32 0xfd6d0ab0 0x44000300 Change-Id: Ia8a2c0f5530c7a056e8d706c651cac1d49b2091c Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldren/gpio.c M src/mainboard/google/brya/variants/uldren/overridetree.cb 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/75644/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/75644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8a2c0f5530c7a056e8d706c651cac1d49b2091c Gerrit-Change-Number: 75644 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7
by Dtrain Hsu (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Shou-Chieh Hsu, Subrata Banik, Tarun Tuli. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75644?usp=email ) Change subject: mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7 ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Is it also disabled in mFIT config (descriptor)? I am not sure which setting you mean? If you mean clockout configuration, yes, it already disable. If no, could you point out the setting in mFIT config? -- To view, visit https://review.coreboot.org/c/coreboot/+/75644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8a2c0f5530c7a056e8d706c651cac1d49b2091c Gerrit-Change-Number: 75644 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Mon, 05 Jun 2023 09:16:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7
by Harsha B R (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Dtrain Hsu, Shou-Chieh Hsu, Subrata Banik, Tarun Tuli. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75644?usp=email ) Change subject: mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7 ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: If you have any test done already (as mentioned in the bug:283735051), that can be added as part of the Test description. -- To view, visit https://review.coreboot.org/c/coreboot/+/75644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8a2c0f5530c7a056e8d706c651cac1d49b2091c Gerrit-Change-Number: 75644 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Mon, 05 Jun 2023 09:05:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7
by Derek Huang (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Dtrain Hsu, Shou-Chieh Hsu, Subrata Banik, Tarun Tuli. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75644?usp=email ) Change subject: mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7 ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: Is it also disabled in mFIT config (descriptor)? -- To view, visit https://review.coreboot.org/c/coreboot/+/75644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8a2c0f5530c7a056e8d706c651cac1d49b2091c Gerrit-Change-Number: 75644 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Mon, 05 Jun 2023 09:03:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/smm: Check the SMM TSEG size
by Paul Menzel (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel, Zheng Bao. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75405?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/amd/smm: Check the SMM TSEG size ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75405/comment/78912724_f0fd7294 : PS4, Line 11: As the datasheet section was already mentioned, please document the source: As per AMD64 Architecture Progrmamer's Manual, section 10.2.5 SMRAM Protected Areas: > The TSeg range must be aligned to a 128 Kbyte boundary and the minimum TSeg size is 128 Kbytes. -- To view, visit https://review.coreboot.org/c/coreboot/+/75405?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4f557c7b77db6fc5ab2783ca4e2ebe7a4476e85 Gerrit-Change-Number: 75405 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Jun 2023 09:00:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/smm: Check the SMM TSEG size
by Himanshu Sahdev (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel, Zheng Bao. Himanshu Sahdev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75405?usp=email ) Change subject: soc/amd/smm: Check the SMM TSEG size ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75405?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4f557c7b77db6fc5ab2783ca4e2ebe7a4476e85 Gerrit-Change-Number: 75405 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Jun 2023 09:00:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/phoenix: Update USB device alias
by Eric Lai (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jon Murphy, Matt DeVillier. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75615?usp=email ) Change subject: soc/amd/phoenix: Update USB device alias ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > If AMD in favor this change, I can update the birman and mayan too. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75615?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1058279fe5b0e3131608a0b9bbd708dbbde7e87 Gerrit-Change-Number: 75615 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Jun 2023 08:55:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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