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Change subject: arch/x86/include/arch/vga: add defines for VGA MMIO addresses
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
using those defines in the x86 soc support can be done later; doing this right now would make the patch train in which this is used even messier as it already is right now
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Change subject: soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt
......................................................................
Patch Set 15:
(1 comment)
File src/soc/amd/common/block/data_fabric/domain.c:
https://review.coreboot.org/c/coreboot/+/74843/comment/4e7febc5_486e760f :
PS14, Line 240: 0x000a0000
> Can we give it a define macro instead a magic value :p
added the defines in CB:75618 and used those in this patch
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Hello Arthur Heymans, Eric Lai, Fred Reitberger, Jason Glenesk, Matt DeVillier, Nico Huber, Raul Rangel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Code-Review+1 by Eric Lai, Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins)
Change subject: soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt
......................................................................
soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt
Generate the PCI0 _CRS ACPI resource template to tell the OS which PCI
bus numbers and IO and MMIO regions can be used for PCI devices below
_SB/PCI0. This data corresponds to what amd_pci_domain_scan_bus and
amd_pci_domain_read_resources provided to the resource allocator. This
makes sure that the PCI0 _CRS ACPI resource template matches the
constraints the resource allocator used when allocating resources.
TEST=With also the rest of the current patch train applied, the
generated _CRS resource template contains the expected PCI bus numbers
and IO and MMIO resources and both Linux and Windows boot on Mandolin.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Iaf6d38a8ef5bb0163c4d1c021bf892c323d9a448
---
M src/soc/amd/common/block/data_fabric/domain.c
M src/soc/amd/common/block/include/amdblocks/data_fabric.h
2 files changed, 95 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/74843/15
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Change subject: soc/intel/xeon_sp/spr: Add RMT config
......................................................................
Patch Set 4: Code-Review+2
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Change subject: vboot: Drop argument to select slot from `vb2ex_ec_protect()`
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Patch Set 6: Code-Review+2
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Change subject: vboot: Drop argument to select slot from `vb2ex_ec_protect()`
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75521/comment/9add1a32_38c26d6b :
PS5, Line 23: w/o this patch
> with this patch?
Acknowledged
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Change subject: vboot: Drop argument to select slot from `vb2ex_ec_protect()`
......................................................................
vboot: Drop argument to select slot from `vb2ex_ec_protect()`
vboot code changes have eliminated the redundant call to WP the EC-RO
region as protecting RW flash implies protecting both RO and RW flash,
so the call to protect RO is redundant. google/rex currently takes
about 17 ms to lock down the EC.
Along with vboot changes, this patch drops argument to choose between
RO and RW slot to protect while calling into `vb2ex_ec_protect()`.
It ensures vb2ex_ec_protect() is explicitly meant for protecting RW
regions.
w/o this patch:
517:waiting for EC to allow higher power draw 846,196 (17,297)
w/ this patch:
517:waiting for EC to allow higher power draw 838,258 (9,719)
Additionally, update vboot submodule to upstream main to avoid the
compilation error.
Updating from commit id 35f50c3154e5:
Fix build error when compiling without -DNDEBUG
to commit id 034907b279c9db:
vboot_reference: eliminate redundant call to write protect EC-RO
Change-Id: I2974f0cb43ba800c2aaeac4876ebaa052b5ee793
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M 3rdparty/vboot
M src/security/vboot/ec_sync.c
2 files changed, 5 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/75521/6
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Change subject: soc/intel/meteorlake: Fill PCI SSID parameters
......................................................................
Patch Set 7: Code-Review+2
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Change subject: soc/amd/mendocino: Print content of manifest file
......................................................................
Patch Set 9: Code-Review+1
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