coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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5387 discussions

[M] Change in coreboot[master]: arch/arm64: Add EL1/EL2/EL3 support for arm64
by Maximilian Brune (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Milosevic, Julius Werner, Lean Sheng Tan, Nico Huber. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74798?usp=email ) Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64 ...................................................................... Patch Set 5: (1 comment) File src/arch/arm64/transition_asm.S: https://review.coreboot.org/c/coreboot/+/74798/comment/9684d1c7_c09f8506 : PS5, Line 155: mrs x1, currentel > No, that one's good the way you wrote it, you should always prefer C `if()` over preprocessor `#if` […] I know its like this in most of our code, but personally I don't understand why I would want to prefer `ìf()` over `#if` It makes more sense to me to use preprocessor directives for things that are known at preprocessor phase (like CONFIG_* variables). Using preprocessor for CONFIG_* variable checking would also get rid of the dead_code macro, since you can just use `#error` right? Seems wrong to depend on the compiler to optimize it out. -- To view, visit https://review.coreboot.org/c/coreboot/+/74798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e Gerrit-Change-Number: 74798 Gerrit-PatchSet: 5 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Mon, 05 Jun 2023 13:44:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/stoneyridge/northbridge: reserve PCI config IO ports
by Felix Held (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75619?usp=email ) Change subject: soc/amd/stoneyridge/northbridge: reserve PCI config IO ports ...................................................................... soc/amd/stoneyridge/northbridge: reserve PCI config IO ports This makes sure that the resource allocator won't use those ports for anything else. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I014ffe3ee94ec153e91113f9a17e89f24ca040b3 --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/75619/1 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 75fdfa4..452a7bb 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -334,6 +334,8 @@ pci_domain_read_resources(dev); + fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); + /* 0x0 -> 0x9ffff */ ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); -- To view, visit https://review.coreboot.org/c/coreboot/+/75619?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I014ffe3ee94ec153e91113f9a17e89f24ca040b3 Gerrit-Change-Number: 75619 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/*/root_complex: reserve PCI config IO ports
by Felix Held (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Eric Lai, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Nico Huber. Hello Eric Lai, Fred Reitberger, Jason Glenesk, Matt DeVillier, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75556?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Code-Review+2 by Eric Lai, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/amd/*/root_complex: reserve PCI config IO ports ...................................................................... soc/amd/*/root_complex: reserve PCI config IO ports This makes sure that the resource allocator won't use those ports for anything else. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie42260902ee2b383dd5867ac813cae029f706f2d --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/root_complex.c 5 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/75556/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/75556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie42260902ee2b383dd5867ac813cae029f706f2d Gerrit-Change-Number: 75556 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/common/smbus: Add support for reading spd data via smbus for DDR5
by Paul Menzel (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Angel Pons, Balaji Manigandan, Kapil Porwal, Karthik Ramasubramanian, Maulik Vaghela, Meera Ravindranath, Nick Vaccaro, Patrick Rudolph, Raj Astekar, Reka Norman, Subrata Banik, Subrata Banik, Tarun Tuli. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52731?usp=email ) Change subject: soc/common/smbus: Add support for reading spd data via smbus for DDR5 ...................................................................... Patch Set 13: (1 comment) File src/soc/intel/common/block/smbus/smbuslib.c: https://review.coreboot.org/c/coreboot/+/52731/comment/487c250a_6ca3fb6c : PS13, Line 54: /* : * By default,an SPD5 hub accepts 1 byte addressing pointing : * to the first 128 bytes of memory. MR11[2:0] selects the page : * pointer to address the entire 1024 bytes of non-volatile memory. : */ Please use one of the recommended multi-line comment styles. -- To view, visit https://review.coreboot.org/c/coreboot/+/52731?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe Gerrit-Change-Number: 52731 Gerrit-PatchSet: 13 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 05 Jun 2023 13:29:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: security/tpm/tspi/log: Respect cbmem TPM log size when copying preram...
by Paul Menzel (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Philipp Deppenwiese, Tim Crawford. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73297?usp=email ) Change subject: security/tpm/tspi/log: Respect cbmem TPM log size when copying preram entries ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/73297/comment/c8a04bbe_9fd699b7 : PS4, Line 11: cmbem CBMEM File src/security/tpm/tspi/log.c: https://review.coreboot.org/c/coreboot/+/73297/comment/b7fbec7f_4ec75d01 : PS4, Line 149: printk(BIOS_ERR, "TPM LOG: log table is full\n"); Also print the values, so it’s documented in the logs? -- To view, visit https://review.coreboot.org/c/coreboot/+/73297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If76299e68eb5ed2ed20c947be35cea46c51fcdec Gerrit-Change-Number: 73297 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 05 Jun 2023 13:27:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/x86/include/arch/vga: add defines for VGA MMIO addresses
by Eric Lai (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75618?usp=email ) Change subject: arch/x86/include/arch/vga: add defines for VGA MMIO addresses ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4a4f39a4e876bbba59620d689cd56c3c286daae Gerrit-Change-Number: 75618 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Jun 2023 13:25:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/x86/include/arch/vga: add defines for VGA MMIO addresses
by Felix Held (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Eric Lai. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75618?usp=email ) Change subject: arch/x86/include/arch/vga: add defines for VGA MMIO addresses ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > you need clean new lines. fixed this and pushed a new version of the patches -- To view, visit https://review.coreboot.org/c/coreboot/+/75618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4a4f39a4e876bbba59620d689cd56c3c286daae Gerrit-Change-Number: 75618 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 05 Jun 2023 13:24:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Remove DDR5 override
by Paul Menzel (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Jeremy Soller, Subrata Banik, Tarun Tuli, Tim Crawford. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75135?usp=email ) Change subject: soc/intel/alderlake: Remove DDR5 override ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75135/comment/dbb15855_473712ad : PS1, Line 9: now Please mention the commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/75135?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedb8f48f70892497d19a7d1b6d8a544080b686e7 Gerrit-Change-Number: 75135 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Mon, 05 Jun 2023 13:24:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/x86/include/arch/vga: add defines for VGA MMIO addresses
by Felix Held (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Eric Lai, Felix Held. Hello Eric Lai, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75618?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Eric Lai, Verified-1 by build bot (Jenkins) Change subject: arch/x86/include/arch/vga: add defines for VGA MMIO addresses ...................................................................... arch/x86/include/arch/vga: add defines for VGA MMIO addresses To avoid magic constants in the code, add defines for the VGA MMIO address range from 0xa0000-0xbffff. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie4a4f39a4e876bbba59620d689cd56c3c286daae --- A src/arch/x86/include/arch/vga.h 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/75618/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4a4f39a4e876bbba59620d689cd56c3c286daae Gerrit-Change-Number: 75618 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: arch/x86/include/arch/vga: add defines for VGA MMIO addresses
by Eric Lai (Code Review) 05 Jun '23

05 Jun '23

Attention is currently required from: Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75618?usp=email ) Change subject: arch/x86/include/arch/vga: add defines for VGA MMIO addresses ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: you need clean new lines. -- To view, visit https://review.coreboot.org/c/coreboot/+/75618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4a4f39a4e876bbba59620d689cd56c3c286daae Gerrit-Change-Number: 75618 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Jun 2023 13:22:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit June 2023