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Change subject: mb/google/rex/var/rex0: probe for i2c1 touchscreen
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> can u please rebase this CL as an independent one ? and we should merge this ASAP.
Done
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Change subject: libpayload/drivers/usb/xhci.c: Check for NULL in xhci_init
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt
......................................................................
Patch Set 17:
(1 comment)
File src/soc/amd/common/block/data_fabric/domain.c:
https://review.coreboot.org/c/coreboot/+/74843/comment/607e8135_3cd7783a :
PS11, Line 169: if (base > PCI_IO_CONFIG_LAST_PORT || limit < PCI_IO_CONFIG_INDEX) {
> Acknowledged
turned out it was the overlap of the resource producer covering the whole io space while the resource consumer for the pci config io ports covered part of the same region in the same acpi pci root device. changed the comment to point that out so that hopefully noone else has to figure this out again
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Change subject: acpi/acpigen: generate DWord IO resource in acpigen_resource_producer_io
......................................................................
Patch Set 3:
(1 comment)
This change is ready for review.
Commit Message:
https://review.coreboot.org/c/coreboot/+/75613/comment/2abb1a2d_db891fe6 :
PS2, Line 18: acpi PNP0A08:00: host bridge window expanded to [io 0x0000-0xffff]; [io 0x0000-0xffff window] ignored
> ok, i tried calling acpigen_resource_dword instead of acpigen_resource_word in acpigen_resource_prod […]
Done
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Hello Arthur Heymans, Eric Lai, Fred Reitberger, Jason Glenesk, Matt DeVillier, Nico Huber, Raul Rangel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74843?usp=email
to look at the new patch set (#17).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt
......................................................................
soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt
Generate the PCI0 _CRS ACPI resource template to tell the OS which PCI
bus numbers and IO and MMIO regions can be used for PCI devices below
_SB/PCI0. This data corresponds to what amd_pci_domain_scan_bus and
amd_pci_domain_read_resources provided to the resource allocator. This
makes sure that the PCI0 _CRS ACPI resource template matches the
constraints the resource allocator used when allocating resources.
TEST=With also the rest of the current patch train applied, the
generated _CRS resource template contains the expected PCI bus numbers
and IO and MMIO resources and both Linux and Windows boot on Mandolin.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Iaf6d38a8ef5bb0163c4d1c021bf892c323d9a448
---
M src/soc/amd/common/block/data_fabric/domain.c
M src/soc/amd/common/block/include/amdblocks/data_fabric.h
2 files changed, 90 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/74843/17
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Change subject: soc/intel/common: Use memcpy library function
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75620/comment/114e17ae_60c5f516 :
PS1, Line 11:
Why is that style preferred?
Is there a difference in the generated code?
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Change subject: device: Add fixed_mem_range_flags() and helpers
......................................................................
Patch Set 16:
(1 comment)
File src/include/device/device.h:
https://review.coreboot.org/c/coreboot/+/55436/comment/8cf05403_7f671767 :
PS16, Line 332: end
i find it rather unintuitive that the end address will be outside of the range being added
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Change subject: device: Add fixed_io_range_flags() and helpers
......................................................................
Patch Set 14:
(1 comment)
File src/include/device/device.h:
https://review.coreboot.org/c/coreboot/+/55458/comment/11c946ff_8808c40c :
PS14, Line 345: end
i find it rather unintuitive that the end address will be outside of the range being added
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Change subject: resource: Add helpers for memory resources
......................................................................
Patch Set 13:
(1 comment)
File src/include/device/device.h:
https://review.coreboot.org/c/coreboot/+/55474/comment/b9d42e05_e0b2a8d5 :
PS13, Line 378: end
i find it rather unintuitive that the end address will be outside of the range being added. same for reserved_ram_from_to
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