coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: mb/google/kukui: Change Juniper/Willow RAM table offset to 0x30
by Felix Held (Code Review) 06 Jun '23

06 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75563?usp=email ) Change subject: mb/google/kukui: Change Juniper/Willow RAM table offset to 0x30 ...................................................................... mb/google/kukui: Change Juniper/Willow RAM table offset to 0x30 All the DRAM module for Juniper/Willow can reuse the RAM ID in offset 0x30 table, so change Juniper/Willow RAM table offset to 0x30 for introducing more DRAM modules. BUG=b:284423187 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I92740275dcc27061a94b7db7ce095655c0bd7cf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75563 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/kukui/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Sheng-Liang Pan: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 86dd8f9..0470899 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -92,7 +92,7 @@ hex default 0x10 if BOARD_GOOGLE_FENNEL || BOARD_GOOGLE_CERISE || BOARD_GOOGLE_STERN || BOARD_GOOGLE_MAKOMO || BOARD_GOOGLE_MUNNA default 0x20 if BOARD_GOOGLE_KAKADU || BOARD_GOOGLE_KATSU - default 0x30 if BOARD_GOOGLE_COZMO || BOARD_GOOGLE_PICO + default 0x30 if BOARD_GOOGLE_COZMO || BOARD_GOOGLE_PICO || BOARD_GOOGLE_JUNIPER || BOARD_GOOGLE_WILLOW default 0x40 if BOARD_GOOGLE_KAPPA default 0x50 if BOARD_GOOGLE_BURNET || BOARD_GOOGLE_ESCHE default 0x0 -- To view, visit https://review.coreboot.org/c/coreboot/+/75563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92740275dcc27061a94b7db7ce095655c0bd7cf5 Gerrit-Change-Number: 75563 Gerrit-PatchSet: 5 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7
by Felix Held (Code Review) 06 Jun '23

06 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75644?usp=email ) Change subject: mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7 ...................................................................... mb/google/nissa/var/uldren: Modify GPP_D7 and PCIE RP7 Uldren does not have PCIE device and should disable PCIE RP7 and GPP_D7 for preventing PCIe controller not power gate in S0ix. BUG=b:283735051 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage 1. PCIE RP7: cbmem -c | grep 'PCI: 00:1c.6' [SPEW ] PCI: 00:1c.6: enabled 0 [SPEW ] PCI: 00:1c.6: enabled 0 2. GPP_D7: iotools mmio_read32 0xfd6d0ab0 0x44000300 Change-Id: Ia8a2c0f5530c7a056e8d706c651cac1d49b2091c Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75644 Reviewed-by: Harsha B R <harsha.b.r(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Derek Huang <derekhuang(a)google.com> --- M src/mainboard/google/brya/variants/uldren/gpio.c M src/mainboard/google/brya/variants/uldren/overridetree.cb 2 files changed, 3 insertions(+), 0 deletions(-) Approvals: Harsha B R: Looks good to me, approved build bot (Jenkins): Verified Derek Huang: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/uldren/gpio.c b/src/mainboard/google/brya/variants/uldren/gpio.c index e1e5e8c..c0c43814 100644 --- a/src/mainboard/google/brya/variants/uldren/gpio.c +++ b/src/mainboard/google/brya/variants/uldren/gpio.c @@ -21,6 +21,8 @@ PAD_CFG_GPO(GPP_C1, 1, DEEP), /* D6 : SRCCLKREQ1# ==> WWAN_EN */ PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* D7 : SRCCLKREQ2# ==> NC */ + PAD_NC(GPP_D7, NONE), /* D8 : SRCCLKREQ3# ==> NC */ PAD_NC(GPP_D8, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ diff --git a/src/mainboard/google/brya/variants/uldren/overridetree.cb b/src/mainboard/google/brya/variants/uldren/overridetree.cb index 77b86552..a873a62 100644 --- a/src/mainboard/google/brya/variants/uldren/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldren/overridetree.cb @@ -353,6 +353,7 @@ end end end + device ref pcie_rp7 off end device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98360A"" -- To view, visit https://review.coreboot.org/c/coreboot/+/75644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8a2c0f5530c7a056e8d706c651cac1d49b2091c Gerrit-Change-Number: 75644 Gerrit-PatchSet: 4 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/rex/variants/ovis: Add RAM IDs
by Felix Held (Code Review) 06 Jun '23

06 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75501?usp=email ) Change subject: mb/google/rex/variants/ovis: Add RAM IDs ...................................................................... mb/google/rex/variants/ovis: Add RAM IDs BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Ic555fac846ebf1e9dad81b5847334c03d6804b5b Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75501 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/ovis/memory/Makefile.inc M src/mainboard/google/rex/variants/ovis/memory/dram_id.generated.txt M src/mainboard/google/rex/variants/ovis/memory/mem_parts_used.txt 3 files changed, 20 insertions(+), 2 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rex/variants/ovis/memory/Makefile.inc b/src/mainboard/google/rex/variants/ovis/memory/Makefile.inc index eace2e4..2083b18 100644 --- a/src/mainboard/google/rex/variants/ovis/memory/Makefile.inc +++ b/src/mainboard/google/rex/variants/ovis/memory/Makefile.inc @@ -1,5 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# ./util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/google/rex/variants/ovis/memory src/mainboard/google/rex/variants/ovis/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 1(0b0001) Parts = MT62F1G32D2DS-026 WT:B, H58G56BK7BX068 +SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 2(0b0010) Parts = MT62F2G32D4DS-026 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 3(0b0011) Parts = K3KL6L60GM-MGCT diff --git a/src/mainboard/google/rex/variants/ovis/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/ovis/memory/dram_id.generated.txt index b243b02..8e84788 100644 --- a/src/mainboard/google/rex/variants/ovis/memory/dram_id.generated.txt +++ b/src/mainboard/google/rex/variants/ovis/memory/dram_id.generated.txt @@ -1,3 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/google/rex/variants/ovis/memory src/mainboard/google/rex/variants/ovis/memory/mem_parts_used.txt DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) +MT62F1G32D2DS-026 WT:B 1 (0001) +MT62F2G32D4DS-026 WT:B 2 (0010) +H58G56BK7BX068 1 (0001) +K3KL6L60GM-MGCT 3 (0011) diff --git a/src/mainboard/google/rex/variants/ovis/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/ovis/memory/mem_parts_used.txt index 9621137..c952558 100644 --- a/src/mainboard/google/rex/variants/ovis/memory/mem_parts_used.txt +++ b/src/mainboard/google/rex/variants/ovis/memory/mem_parts_used.txt @@ -9,3 +9,8 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +MT62F512M32D2DR-031 WT:B +MT62F1G32D2DS-026 WT:B +MT62F2G32D4DS-026 WT:B +H58G56BK7BX068 +K3KL6L60GM-MGCT -- To view, visit https://review.coreboot.org/c/coreboot/+/75501?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic555fac846ebf1e9dad81b5847334c03d6804b5b Gerrit-Change-Number: 75501 Gerrit-PatchSet: 6 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: mb/google/rex: Create ovis variant
by Felix Held (Code Review) 06 Jun '23

06 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75385?usp=email ) Change subject: mb/google/rex: Create ovis variant ...................................................................... mb/google/rex: Create ovis variant BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a ; Make sure GOOGLE_OVIS built successfully Change-Id: I5c8f290cfdcb4d47c0e5e9d72c1e34073b957681 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75385 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/Kconfig.name A src/mainboard/google/rex/variants/baseboard/ovis/Makefile.inc A src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb A src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/ec.h A src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/gpio.h A src/mainboard/google/rex/variants/baseboard/ovis/memory.c A src/mainboard/google/rex/variants/ovis/Makefile.inc A src/mainboard/google/rex/variants/ovis/gpio.c A src/mainboard/google/rex/variants/ovis/include/variant/ec.h A src/mainboard/google/rex/variants/ovis/include/variant/gpio.h A src/mainboard/google/rex/variants/ovis/memory/Makefile.inc A src/mainboard/google/rex/variants/ovis/memory/dram_id.generated.txt A src/mainboard/google/rex/variants/ovis/memory/mem_parts_used.txt A src/mainboard/google/rex/variants/ovis/overridetree.cb 15 files changed, 349 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 4021fce..bec7cb6 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -43,11 +43,24 @@ select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 +config BOARD_GOOGLE_BASEBOARD_OVIS + def_bool n + select BOARD_GOOGLE_REX_COMMON + select DRIVERS_INTEL_PMC + select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP + select HAVE_SLP_S0_GATE + select MAINBOARD_HAS_CHROMEOS + select MEMORY_SOLDERDOWN + select SOC_INTEL_METEORLAKE + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select TPM_GOOGLE_TI50 + if BOARD_GOOGLE_REX_COMMON config BASEBOARD_DIR string default "rex" if BOARD_GOOGLE_BASEBOARD_REX + default "ovis" if BOARD_GOOGLE_BASEBOARD_OVIS config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES @@ -79,17 +92,20 @@ config MAINBOARD_FAMILY string default "Google_Rex" if BOARD_GOOGLE_BASEBOARD_REX + default "Google_Ovis" if BOARD_GOOGLE_BASEBOARD_OVIS config MAINBOARD_PART_NUMBER default "Rex" if BOARD_GOOGLE_REX0 || BOARD_GOOGLE_REX_EC_ISH default "Screebo" if BOARD_GOOGLE_SCREEBO default "Karis" if BOARD_GOOGLE_KARIS + default "Ovis" if BOARD_GOOGLE_OVIS config VARIANT_DIR string default "rex0" if BOARD_GOOGLE_REX0 || BOARD_GOOGLE_REX_EC_ISH default "screebo" if BOARD_GOOGLE_SCREEBO default "karis" if BOARD_GOOGLE_KARIS + default "ovis" if BOARD_GOOGLE_OVIS config DIMM_SPD_SIZE default 512 @@ -112,7 +128,7 @@ config DRIVER_TPM_I2C_BUS hex - default 0x4 if BOARD_GOOGLE_REX0 || BOARD_GOOGLE_SCREEBO || BOARD_GOOGLE_REX_EC_ISH + default 0x4 if BOARD_GOOGLE_REX0 || BOARD_GOOGLE_SCREEBO || BOARD_GOOGLE_REX_EC_ISH || BOARD_GOOGLE_OVIS config DRIVER_TPM_I2C_ADDR hex diff --git a/src/mainboard/google/rex/Kconfig.name b/src/mainboard/google/rex/Kconfig.name index 13a0447..8084a04 100644 --- a/src/mainboard/google/rex/Kconfig.name +++ b/src/mainboard/google/rex/Kconfig.name @@ -28,3 +28,7 @@ select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_SOUNDWIRE_CS42L42 select DRIVERS_SOUNDWIRE_MAX98363 + +config BOARD_GOOGLE_OVIS + bool "-> Ovis" + select BOARD_GOOGLE_BASEBOARD_OVIS diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/Makefile.inc b/src/mainboard/google/rex/variants/baseboard/ovis/Makefile.inc new file mode 100644 index 0000000..fd45b94 --- /dev/null +++ b/src/mainboard/google/rex/variants/baseboard/ovis/Makefile.inc @@ -0,0 +1 @@ +romstage-y += memory.c diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb new file mode 100644 index 0000000..9a71e95 --- /dev/null +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -0,0 +1,69 @@ +chip soc/intel/meteorlake + + # GPE configuration + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_E" + register "pmc_gpe0_dw2" = "GPP_F" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 2 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 3 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 4 + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 5 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6 + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7 + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 8 + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 9 + + register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 0 + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 1 + + register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 0 + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 1 + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2 + register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3 + + # S0ix enable + register "s0ix_enable" = "1" + + # DPTF enable + register "dptf_enable" = "1" + + # Enable CNVi BT + register "cnvi_bt_core" = "true" + + # Set on-board graphics as primary display + register "skip_ext_gfx_scan" = "1" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + + device domain 0 on + device ref igpu on end + device ref dtt on end + device ref xhci on end + device ref shared_sram on end + device ref heci1 on end + device ref uart0 on end + device ref soc_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + end +end diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/ec.h b/src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/ec.h new file mode 100644 index 0000000..a0f47d9 --- /dev/null +++ b/src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/ec.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <baseboard/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_NONE) +/* EC can wake from S5 with power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) +/* + * EC can wake from S3/S0ix with: + * 1. AC Connect/Disconnect + * 2. Power button + * 3. Key press + * 4. Mode change + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) +/* + * ACPI related definitions for ASL code. + */ +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/gpio.h b/src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/gpio.h new file mode 100644 index 0000000..35e055b --- /dev/null +++ b/src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/gpio.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* WP signal to PCH */ +#define GPIO_PCH_WP GPP_H10 +/* GPIO IRQ for tight timestamps / wake support */ +#define EC_SYNC_IRQ GPP_A17_IRQ +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI +/* Used to gate SoC's SLP_S0# signal */ +#define GPIO_SLP_S0_GATE GPP_H14 +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_E11 +#define GPIO_MEM_CONFIG_1 GPP_E02 +#define GPIO_MEM_CONFIG_2 GPP_E01 +#define GPIO_MEM_CONFIG_3 GPP_E12 +#define GPIO_MEM_CH_SEL GPP_E13 + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/memory.c b/src/mainboard/google/rex/variants/baseboard/ovis/memory.c new file mode 100644 index 0000000..1541cec --- /dev/null +++ b/src/mainboard/google/rex/variants/baseboard/ovis/memory.c @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-3.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 7, 1, 2, 0, 3, 6, 5, 4 }, + .dq1 = { 13, 12, 14, 15, 8, 9, 10, 11 }, + }, + .ddr1 = { + .dq0 = { 10, 9, 11, 8, 15, 13, 14, 12 }, + .dq1 = { 6, 0, 7, 4, 3, 1, 2, 5 }, + }, + .ddr2 = { + .dq0 = { 11, 10, 8, 9, 12, 15, 14, 13 }, + .dq1 = { 7, 0, 6, 5, 3, 2, 1, 4 }, + }, + .ddr3 = { + .dq0 = { 13, 10, 8, 9, 14, 11, 15, 12 }, + .dq1 = { 1, 6, 4, 7, 0, 5, 2, 3 }, + }, + .ddr4 = { + .dq0 = { 10, 11, 9, 12, 13, 14, 15, 8 }, + .dq1 = { 6, 7, 4, 5, 1, 0, 3, 2 }, + }, + .ddr5 = { + .dq0 = { 0, 5, 3, 6, 1, 4, 2, 7 }, + .dq1 = { 8, 11, 10, 9, 15, 14, 13, 12 }, + }, + .ddr6 = { + .dq0 = { 1, 3, 0, 2, 6, 5, 7, 4 }, + .dq1 = { 13, 15, 14, 12, 11, 10, 8, 9 }, + }, + .ddr7 = { + .dq0 = { 10, 9, 11, 8, 12, 15, 14, 13 }, + .dq1 = { 6, 4, 7, 5, 2, 1, 0, 3 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, + }, + + .lp5x_config = { + .ccc_config = 0x66, + }, + + .ect = 1, /* Early Command Training */ +}; + +const struct mb_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int __weak variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool __weak variant_is_half_populated(void) +{ + return gpio_get(GPIO_MEM_CH_SEL); +} + +void __weak variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} diff --git a/src/mainboard/google/rex/variants/ovis/Makefile.inc b/src/mainboard/google/rex/variants/ovis/Makefile.inc new file mode 100644 index 0000000..2fa692a --- /dev/null +++ b/src/mainboard/google/rex/variants/ovis/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/rex/variants/ovis/gpio.c b/src/mainboard/google/rex/variants/ovis/gpio.c new file mode 100644 index 0000000..b6e346f --- /dev/null +++ b/src/mainboard/google/rex/variants/ovis/gpio.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <types.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +static const struct cros_gpio cros_gpios[] = { +}; + +DECLARE_CROS_GPIOS(cros_gpios); + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/rex/variants/ovis/include/variant/ec.h b/src/mainboard/google/rex/variants/ovis/include/variant/ec.h new file mode 100644 index 0000000..4fc0622 --- /dev/null +++ b/src/mainboard/google/rex/variants/ovis/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/rex/variants/ovis/include/variant/gpio.h b/src/mainboard/google/rex/variants/ovis/include/variant/gpio.h new file mode 100644 index 0000000..27c87b3 --- /dev/null +++ b/src/mainboard/google/rex/variants/ovis/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <baseboard/gpio.h> + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/rex/variants/ovis/memory/Makefile.inc b/src/mainboard/google/rex/variants/ovis/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/rex/variants/ovis/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/rex/variants/ovis/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/ovis/memory/dram_id.generated.txt new file mode 100644 index 0000000..b243b02 --- /dev/null +++ b/src/mainboard/google/rex/variants/ovis/memory/dram_id.generated.txt @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +DRAM Part Name ID to assign diff --git a/src/mainboard/google/rex/variants/ovis/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/ovis/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/rex/variants/ovis/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb new file mode 100644 index 0000000..b68840f --- /dev/null +++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/meteorlake + device domain 0 on + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/75385?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c8f290cfdcb4d47c0e5e9d72c1e34073b957681 Gerrit-Change-Number: 75385 Gerrit-PatchSet: 9 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Dabros <dabros(a)google.com> Gerrit-CC: Jan Dabros <jsd(a)semihalf.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[master]: mb/google/corsola/var/starmie: Add K&D-ILI9882T panel support
by Felix Held (Code Review) 06 Jun '23

06 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75479?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/corsola/var/starmie: Add K&D-ILI9882T panel support ...................................................................... mb/google/corsola/var/starmie: Add K&D-ILI9882T panel support The K&D-ILI9882T panel and STA-ILI9882T share all DCS commands and EDID information except for the manufacturer_name which has no effect to the function of panel. Let's reuse the STA_ILI9882T struct in this case. BUG=None TEST=emerge-staryu coreboot chromeos-bootimage and boot the panel Signed-off-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Change-Id: I510462a49d273f3d25158b25906d4c514f855cdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/75479 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/corsola/panel_starmie.c 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/corsola/panel_starmie.c b/src/mainboard/google/corsola/panel_starmie.c index aadabf4..9306960 100644 --- a/src/mainboard/google/corsola/panel_starmie.c +++ b/src/mainboard/google/corsola/panel_starmie.c @@ -38,11 +38,20 @@ } static struct panel_description starmie_panels[] = { + /* K&D panel vendor and ILI9882T chip, + K&D and STA panel are identical except manufacturer_name. */ + [3] = { + .power_on = mipi_panel_power_on, + .name = "STA_ILI9882T", + .orientation = LB_FB_ORIENTATION_LEFT_UP, + }, + /* STA panel vendor and ILI9882T chip */ [8] = { .power_on = mipi_panel_power_on, .name = "STA_ILI9882T", .orientation = LB_FB_ORIENTATION_LEFT_UP, }, + /* STA panel vendor and HIMAX83102_J02 chip */ [10] = { .power_on = mipi_panel_power_on, .name = "STA_HIMAX83102_J02", -- To view, visit https://review.coreboot.org/c/coreboot/+/75479?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I510462a49d273f3d25158b25906d4c514f855cdf Gerrit-Change-Number: 75479 Gerrit-PatchSet: 8 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: mb/google/geralt: Fix MIPI panel power on/off sequence
by Felix Held (Code Review) 06 Jun '23

06 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75512?usp=email ) Change subject: mb/google/geralt: Fix MIPI panel power on/off sequence ...................................................................... mb/google/geralt: Fix MIPI panel power on/off sequence Based on the power sequence of the panel [1], the power on T2 sequence VSP to VSN should be larger than 1ms, and the power off T2 sequence VSP to VSN should be larger than 0ms. We modify the power sequence to meet the datasheet requirement. [1] B5 TV110C9M-LL0 Product Specification Rev.P0 Signed-off-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Change-Id: I4ccb5be04062a0516f84a054ff3f40afbf5279be Reviewed-on: https://review.coreboot.org/c/coreboot/+/75512 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/geralt/display.c M src/mainboard/google/geralt/display.h M src/mainboard/google/geralt/panel.c M src/mainboard/google/geralt/panel.h M src/mainboard/google/geralt/panel_geralt.c M src/soc/mediatek/mt8188/Makefile.inc 6 files changed, 18 insertions(+), 71 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/mainboard/google/geralt/display.c b/src/mainboard/google/geralt/display.c index 8c7a0c1..fa007a1 100644 --- a/src/mainboard/google/geralt/display.c +++ b/src/mainboard/google/geralt/display.c @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <assert.h> #include <console/console.h> #include <delay.h> -#include <device/i2c_simple.h> #include <edid.h> #include <framebuffer_info.h> #include <gpio.h> @@ -11,16 +9,12 @@ #include <soc/dptx.h> #include <soc/dsi.h> #include <soc/gpio_common.h> -#include <soc/i2c.h> #include <soc/mtcmos.h> #include "display.h" #include "gpio.h" #include "panel.h" -#define PMIC_TPS65132_I2C I2C3 -#define PMIC_TPS65132_SLAVE 0x3E - int configure_display(void) { struct edid edid; @@ -78,44 +72,3 @@ return 0; } - -void tps65132s_program_eeprom(void) -{ - u8 value = 0; - u8 value1 = 0; - - /* Initialize I2C3 for PMIC TPS65132 */ - mtk_i2c_bus_init(PMIC_TPS65132_I2C, I2C_SPEED_FAST); - mdelay(10); - - gpio_output(GPIO_EN_PPVAR_MIPI_DISP, 1); - gpio_output(GPIO_EN_PPVAR_MIPI_DISP_150MA, 1); - mdelay(10); - - i2c_read_field(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x00, &value, 0xFF, 0); - i2c_read_field(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x01, &value1, 0xFF, 0); - - if (value != 0x11 || value1 != 0x11) { - printk(BIOS_INFO, "Just set AVDD AVEE 5.7V to EEPROM Data in first time.\n"); - - /* Set AVDD = 5.7V */ - if (panel_pmic_reg_mask(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x00, 0x11, - 0x1F) < 0) - return; - - /* Set AVEE = -5.7V */ - if (panel_pmic_reg_mask(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x01, 0x11, - 0x1F) < 0) - return; - - /* Set EEPROM Data */ - if (panel_pmic_reg_mask(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0xFF, 0x80, - 0xFC) < 0) - return; - mdelay(50); - } - - gpio_output(GPIO_EN_PPVAR_MIPI_DISP, 0); - gpio_output(GPIO_EN_PPVAR_MIPI_DISP_150MA, 0); - mdelay(5); -} diff --git a/src/mainboard/google/geralt/display.h b/src/mainboard/google/geralt/display.h index 71e0e08..29153b3 100644 --- a/src/mainboard/google/geralt/display.h +++ b/src/mainboard/google/geralt/display.h @@ -4,6 +4,5 @@ #define __MAINBOARD_GOOGLE_GERALT_DISPLAY_H__ int configure_display(void); -void tps65132s_program_eeprom(void); #endif diff --git a/src/mainboard/google/geralt/panel.c b/src/mainboard/google/geralt/panel.c index 78d4f84..3174870 100644 --- a/src/mainboard/google/geralt/panel.c +++ b/src/mainboard/google/geralt/panel.c @@ -3,7 +3,6 @@ #include <boardid.h> #include <cbfs.h> #include <console/console.h> -#include <device/i2c_simple.h> #include <edid.h> #include <gpio.h> #include <soc/gpio_common.h> @@ -12,21 +11,6 @@ #include "gpio.h" #include "panel.h" -int panel_pmic_reg_mask(u32 bus, u8 chip, u8 addr, u8 val, u8 mask) -{ - u8 msg = 0; - - if (i2c_read_field(bus, chip, addr, &msg, 0xFF, 0) < 0) { - printk(BIOS_ERR, "Failed to read i2c: addr(%u)\n", addr); - return -1; - } - - msg &= ~mask; - msg |= val; - - return i2c_write_field(bus, chip, addr, msg, 0xFF, 0); -} - static void get_mipi_cmd_from_cbfs(struct panel_description *desc) { /* diff --git a/src/mainboard/google/geralt/panel.h b/src/mainboard/google/geralt/panel.h index 0335ece..11b7fb0 100644 --- a/src/mainboard/google/geralt/panel.h +++ b/src/mainboard/google/geralt/panel.h @@ -17,7 +17,6 @@ }; void fill_lp_backlight_gpios(struct lb_gpios *gpios); -int panel_pmic_reg_mask(u32 bus, u8 chip, u8 addr, u8 val, u8 mask); uint32_t panel_id(void); struct panel_description *get_panel_description(uint32_t panel_id); struct panel_description *get_active_panel(void); diff --git a/src/mainboard/google/geralt/panel_geralt.c b/src/mainboard/google/geralt/panel_geralt.c index 159bc76..9a98836 100644 --- a/src/mainboard/google/geralt/panel_geralt.c +++ b/src/mainboard/google/geralt/panel_geralt.c @@ -8,6 +8,7 @@ #include <soc/gpio_common.h> #include <soc/i2c.h> #include <soc/regulator.h> +#include <soc/tps65132s.h> #include <soc/pmif.h> #include <string.h> @@ -15,6 +16,7 @@ #include "gpio.h" #include "panel.h" +#define PMIC_TPS65132_I2C I2C3 static void configure_mipi_pwm_backlight(void) { @@ -29,17 +31,26 @@ static void power_on_mipi_boe_tv110c9m_ll0(void) { - tps65132s_program_eeprom(); + const struct tps65132s_reg_setting reg_settings[] = { + { PMIC_TPS65132_VPOS, 0x11, 0x1f }, + { PMIC_TPS65132_VNEG, 0x11, 0x1f }, + { PMIC_TPS65132_DLYX, 0x95, 0xff }, + { PMIC_TPS65132_ASSDD, 0x5b, 0xff }, + }; + const struct tps65132s_cfg cfg = { + .i2c_bus = PMIC_TPS65132_I2C, + .en = GPIO_EN_PPVAR_MIPI_DISP, + .sync = GPIO_EN_PPVAR_MIPI_DISP_150MA, + .settings = reg_settings, + .setting_counts = ARRAY_SIZE(reg_settings), + }; /* Enable VM18V */ mainboard_enable_regulator(MTK_REGULATOR_VDD18, true); - + if (tps65132s_setup(&cfg) != CB_SUCCESS) + printk(BIOS_ERR, "Failed to set up voltage regulator tps65132s\n"); gpio_output(GPIO_DISP_RST_1V8_L, 0); mdelay(1); - - gpio_output(GPIO_EN_PPVAR_MIPI_DISP, 1); - gpio_output(GPIO_EN_PPVAR_MIPI_DISP_150MA, 1); - mdelay(10); gpio_output(GPIO_DISP_RST_1V8_L, 1); mdelay(1); gpio_output(GPIO_DISP_RST_1V8_L, 0); diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index 651cff0..67c2d7a 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -55,6 +55,7 @@ ramstage-y += soc.c ramstage-y += ../common/spm.c spm.c ramstage-y += ../common/sspm.c +ramstage-y += ../common/tps65132s.c ramstage-y += ../common/usb.c usb.c BL31_MAKEARGS += PLAT=mt8188 -- To view, visit https://review.coreboot.org/c/coreboot/+/75512?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ccb5be04062a0516f84a054ff3f40afbf5279be Gerrit-Change-Number: 75512 Gerrit-PatchSet: 5 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/meteorlake: Fill PCI SSID parameters
by Felix Held (Code Review) 06 Jun '23

06 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71643?usp=email ) Change subject: soc/intel/meteorlake: Fill PCI SSID parameters ...................................................................... soc/intel/meteorlake: Fill PCI SSID parameters Set SSID UPD to program DID as SSID for all the on board PCIe devices if SSID is not being overridden by CONFIG option or device tree. BUG=b:263846223 TEST=Verify that SSID for all PCI devices is same as their respective DIDs. Output of lspci in the OS: 00:00.0 0600: 8086:7d02 (rev 01) Subsystem: 8086:7d02 00:02.0 0300: 8086:7d45 (prog-if 00 [VGA controller]) Subsystem: 8086:7d45 00:04.0 1180: 8086:7d03 (rev 01) Subsystem: 8086:7d03 00:05.0 0480: 8086:7d19 (rev 01) Subsystem: 8086:7d19 00:06.0 0604: 8086:7e4d (rev 01) (prog-if 00 [Normal decode]) Subsystem: 8086:7e4d Capabilities: [98] Subsystem: 8086:7e4d 00:07.0 0604: 8086:7ec4 (prog-if 00 [Normal decode]) Subsystem: 8086:7ec4 Capabilities: [90] Subsystem: 8086:7ec4 00:07.2 0604: 8086:7ec6 (prog-if 00 [Normal decode]) Subsystem: 8086:7ec6 Capabilities: [90] Subsystem: 8086:7ec6 00:0a.0 1180: 8086:7d0d (rev 01) Subsystem: 8086:7d0d 00:0d.0 0c03: 8086:7ec0 (prog-if 30 [XHCI]) Subsystem: 8086:7ec0 00:0d.2 0c03: 8086:7ec2 (prog-if 40) Subsystem: 8086:7ec2 00:0d.3 0c03: 8086:7ec3 (prog-if 40) Subsystem: 8086:7ec3 00:14.0 0c03: 8086:7e7d (rev 01) (prog-if 30 [XHCI]) Subsystem: 8086:7e7d 00:14.2 0500: 8086:7e7f (rev 01) Subsystem: 8086:7e7f 00:14.3 0280: 8086:7e40 (rev 01) Subsystem: 8086:0094 00:15.0 0c80: 8086:7e78 (rev 01) Subsystem: 8086:7e78 00:15.1 0c80: 8086:7e79 (rev 01) Subsystem: 8086:7e79 00:15.3 0c80: 8086:7e7b (rev 01) Subsystem: 8086:7e7b 00:16.0 0780: 8086:7e70 (rev 01) Subsystem: 8086:7e70 00:19.0 0c80: 8086:7e50 (rev 01) Subsystem: 8086:7e50 00:19.1 0c80: 8086:7e51 (rev 01) Subsystem: 8086:7e51 00:1c.0 0604: 8086:7e3e (rev 01) (prog-if 00 [Normal decode]) Subsystem: 8086:7e3e Capabilities: [98] Subsystem: 8086:7e3e 00:1e.0 0780: 8086:7e25 (rev 01) Subsystem: 8086:7e25 00:1e.3 0c80: 8086:7e30 (rev 01) Subsystem: 8086:7e30 00:1f.0 0601: 8086:7e04 (rev 01) Subsystem: 8086:7e04 00:1f.3 0401: 8086:7e28 (rev 01) 00:1f.5 0c80: 8086:7e23 (rev 01) Subsystem: 8086:7e23 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I364c2052984b6f562bffe8f5ad7035c8b659d369 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71643 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/fsp_params.c 1 file changed, 67 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index eff8176..790bf9c 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -42,6 +42,8 @@ #define DEF_DMVAL 15 #define DEF_DITOVAL 625 +#define MAX_ONBOARD_PCIE_DEVICES 256 + static const struct slot_irq_constraints irq_constraints[] = { { .slot = PCI_DEV_SLOT_PCIE_3, @@ -701,6 +703,70 @@ fsp_debug_event_handler; } +static void evaluate_ssid(const struct device *dev, uint16_t *svid, uint16_t *ssid) +{ + if (!(dev && svid && ssid)) + return; + + *svid = CONFIG_SUBSYSTEM_VENDOR_ID ? : (dev->subsystem_vendor ? : 0x8086); + *ssid = CONFIG_SUBSYSTEM_DEVICE_ID ? : (dev->subsystem_device ? : 0xfffe); +} + +/* + * Programming SSID before FSP-S is important because SSID registers of a few PCIE + * devices (e.g. IPU, Crashlog, XHCI, TCSS_XHCI etc.) are locked after FSP-S hence + * provide a custom SSID (same as DID by default) value via UPD. + */ +static void fill_fsps_pci_ssid_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_meteorlake_config *config) +{ + struct svid_ssid_init_entry { + union { + struct { + uint64_t reg:12; + uint64_t function:3; + uint64_t device:5; + uint64_t bus:8; + uint64_t ignore1:4; + uint64_t segment:16; + uint64_t ignore2:16; + }; + uint64_t data; + }; + struct { + uint16_t svid; + uint16_t ssid; + }; + uint32_t ignore3; + }; + + static struct svid_ssid_init_entry ssid_table[MAX_ONBOARD_PCIE_DEVICES]; + const struct device *dev; + int i = 0; + + for (dev = all_devices; dev; dev = dev->next) { + if (!(is_dev_enabled(dev) && dev->path.type == DEVICE_PATH_PCI && + dev->bus->secondary == 0)) + continue; + + if (dev->path.pci.devfn == PCI_DEVFN_ROOT) { + evaluate_ssid(dev, &s_cfg->SiCustomizedSvid, &s_cfg->SiCustomizedSsid); + } else { + ssid_table[i].reg = PCI_SUBSYSTEM_VENDOR_ID; + ssid_table[i].device = PCI_SLOT(dev->path.pci.devfn); + ssid_table[i].function = PCI_FUNC(dev->path.pci.devfn); + evaluate_ssid(dev, &ssid_table[i].svid, &ssid_table[i].ssid); + i++; + } + } + + s_cfg->SiSsidTablePtr = (uintptr_t)ssid_table; + s_cfg->SiNumberOfSsidTableEntry = i; + + /* Ensure FSP will program the registers */ + s_cfg->SiSkipSsidProgramming = 0; +} + static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, struct soc_intel_meteorlake_config *config) { @@ -730,6 +796,7 @@ fill_fsps_ufs_params, fill_fsps_ai_params, fill_fsps_irq_params, + fill_fsps_pci_ssid_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) -- To view, visit https://review.coreboot.org/c/coreboot/+/71643?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I364c2052984b6f562bffe8f5ad7035c8b659d369 Gerrit-Change-Number: 71643 Gerrit-PatchSet: 8 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt
by Nico Huber (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Arthur Heymans, Eric Lai, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74843?usp=email ) Change subject: soc/amd/common/data_fabric/domain: provide amd_pci_domain_fill_ssdt ...................................................................... Patch Set 18: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74843?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf6d38a8ef5bb0163c4d1c021bf892c323d9a448 Gerrit-Change-Number: 74843 Gerrit-PatchSet: 18 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Jun 2023 12:13:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/nissa/var/joxer: disable PCIE RP7
by Mark Hsieh (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Felix Held, Henry Sun, Mark Hsieh, Paul Fagerburg, Reka Norman, Shou-Chieh Hsu, Tarun Tuli. Hello Eric Lai, Felix Held, Henry Sun, Paul Fagerburg, Paul Menzel, Reka Norman, Shou-Chieh Hsu, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75658?usp=email to look at the new patch set (#5). Change subject: mb/google/nissa/var/joxer: disable PCIE RP7 ...................................................................... mb/google/nissa/var/joxer: disable PCIE RP7 joxer removed SD card from all SKUs, thus disable pcie_rp7. BUG=b:285477026 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Change-Id: I3486d665ddb1de521ab4e656addb2209055174c7 --- M src/mainboard/google/brya/variants/joxer/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/75658/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/75658?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3486d665ddb1de521ab4e656addb2209055174c7 Gerrit-Change-Number: 75658 Gerrit-PatchSet: 5 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/common/data_fabric/domain: provide scan_bus and read_resources
by Nico Huber (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74717?usp=email ) Change subject: soc/amd/common/data_fabric/domain: provide scan_bus and read_resources ...................................................................... Patch Set 17: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4aada7c8a2a43145ad08d11d0a38d9cdc182b98e Gerrit-Change-Number: 74717 Gerrit-PatchSet: 17 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Jun 2023 12:08:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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