coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[master]: soc/amd/common/block/cpu/noncar/cpu: add missing types.h include
by Raul Rangel (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75622?usp=email ) Change subject: soc/amd/common/block/cpu/noncar/cpu: add missing types.h include ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75622?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I875e3bb096b56bbea862c9ad0e3e14e025e3298b Gerrit-Change-Number: 75622 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Jun 2023 16:22:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/stoneyridge/northbridge: reserve PCI config IO ports
by Raul Rangel (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Felix Held, Matt DeVillier. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75619?usp=email ) Change subject: soc/amd/stoneyridge/northbridge: reserve PCI config IO ports ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75619?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I014ffe3ee94ec153e91113f9a17e89f24ca040b3 Gerrit-Change-Number: 75619 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Jun 2023 16:22:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/*/root_complex: reserve PCI config IO ports
by Raul Rangel (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Eric Lai, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75556?usp=email ) Change subject: soc/amd/*/root_complex: reserve PCI config IO ports ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie42260902ee2b383dd5867ac813cae029f706f2d Gerrit-Change-Number: 75556 Gerrit-PatchSet: 9 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Jun 2023 16:22:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Enable fingerprint on UART
by Eric Lai (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Jon Murphy, Karthik Ramasubramanian, Paul Menzel, Tim Van Patten. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75629?usp=email ) Change subject: mb/google/myst: Enable fingerprint on UART ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/myst/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/75629/comment/02030ee2_87adaa3a : PS3, Line 71: PAD_GPO(GPIO_40, LOW), > Is there a HW spec requirement for how long the line must stay asserted? […] Micheal said we should keep it low durning boot. You can check the chat. -- To view, visit https://review.coreboot.org/c/coreboot/+/75629?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09819037b80e55edeb56faef9e27fe0753748efc Gerrit-Change-Number: 75629 Gerrit-PatchSet: 3 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 06 Jun 2023 16:10:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Enable fingerprint on UART
by Tim Van Patten (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Eric Lai, Jon Murphy, Karthik Ramasubramanian, Paul Menzel. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75629?usp=email ) Change subject: mb/google/myst: Enable fingerprint on UART ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/myst/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/75629/comment/c620141e_d80db422 : PS3, Line 71: PAD_GPO(GPIO_40, LOW), Is there a HW spec requirement for how long the line must stay asserted? My understanding is that we use `generic.reset_delay_ms` in the device tree to explicitly control how long we keep the reset signal toggled during boot to satisfy any HW requirements. Otherwise, there's no guarantee that the line is asserted long enough in both the cold boot and cold reset cases. -- To view, visit https://review.coreboot.org/c/coreboot/+/75629?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09819037b80e55edeb56faef9e27fe0753748efc Gerrit-Change-Number: 75629 Gerrit-PatchSet: 3 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 06 Jun 2023 16:01:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: libpayload/drivers/usb/xhci.c: Check for NULL in xhci_init
by Fred Reitberger (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger. Hello Felix Held, Jon Murphy, Karthik Ramasubramanian, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75645?usp=email to look at the new patch set (#2). Change subject: libpayload/drivers/usb/xhci.c: Check for NULL in xhci_init ...................................................................... libpayload/drivers/usb/xhci.c: Check for NULL in xhci_init Ensure the physical_bar parameter passed to xhci_init is not NULL, else return NULL. BUG=b:284213001 Change-Id: I05c32612606793adcba3f4a5724092387a215d41 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M payloads/libpayload/drivers/usb/xhci.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/75645/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75645?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05c32612606793adcba3f4a5724092387a215d41 Gerrit-Change-Number: 75645 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/google/myst: Correct CROS_WP_GPIO to active high
by Tim Van Patten (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Eric Lai, Karthik Ramasubramanian. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75628?usp=email ) Change subject: mb/google/myst: Correct CROS_WP_GPIO to active high ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75628?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54c578e5df5f1b24743cc9506e1e31b0b18bfb25 Gerrit-Change-Number: 75628 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 06 Jun 2023 15:52:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/x86/include/arch/vga: add defines for VGA MMIO addresses
by Felix Held (Code Review) 06 Jun '23

06 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75618?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch/x86/include/arch/vga: add defines for VGA MMIO addresses ...................................................................... arch/x86/include/arch/vga: add defines for VGA MMIO addresses To avoid magic constants in the code, add defines for the VGA MMIO address range from 0xa0000-0xbffff. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie4a4f39a4e876bbba59620d689cd56c3c286daae Reviewed-on: https://review.coreboot.org/c/coreboot/+/75618 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/arch/x86/include/arch/vga.h 1 file changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/arch/x86/include/arch/vga.h b/src/arch/x86/include/arch/vga.h new file mode 100644 index 0000000..b82d635 --- /dev/null +++ b/src/arch/x86/include/arch/vga.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef ARCH_X86_VGA_H +#define ARCH_X86_VGA_H + +/* VGA MMIO and SMM ASEG share the same address range */ +#define VGA_MMIO_BASE 0xa0000 +#define VGA_MMIO_SIZE 0x20000 +#define VGA_MMIO_LIMIT (VGA_MMIO_BASE + VGA_MMIO_SIZE - 1) + +#endif /* ARCH_X86_VGA_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/75618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4a4f39a4e876bbba59620d689cd56c3c286daae Gerrit-Change-Number: 75618 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/smm: Check the SMM TSEG size
by Himanshu Sahdev (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Arthur Heymans, Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Paul Menzel, Raul Rangel, Zheng Bao. Himanshu Sahdev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75405?usp=email ) Change subject: soc/amd/smm: Check the SMM TSEG size ...................................................................... Patch Set 6: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75405/comment/1443c3f1_115a49e5 : PS3, Line 10: The SMM TSEG size should be less than SMM reserved size, bigger than : 8M, and power of 2. > I can not find the solid proof that it should be power of 2. > I checked the AGESA and platform code. They do use the value of power of 2 but don't say why. https://edc.intel.com/content/www/us/en/design/publications/12th-generation… As per this intel datasheet: ``` NOTE: BIOS must program TSEGMB to a 8MB naturally aligned boundary. ``` ^This seems the reason for the extra sanity check of 8 MB within ${src}/cpu/intel/model_2065x/model_2065x.h alike instances. About power of 2: Alignment of an address depends on the power of 2. An address is aligned to X(chosen power of 2) if its alignment is Xn+0. Though a datum is naturally aligned if its address is aligned to its size. (Please correct me if I am wrong)The reason here is the alignment!? -- To view, visit https://review.coreboot.org/c/coreboot/+/75405?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4f557c7b77db6fc5ab2783ca4e2ebe7a4476e85 Gerrit-Change-Number: 75405 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Jun 2023 15:33:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mainboard/google: move tpm_tis to AMD common code
by Raul Rangel (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Grzegorz Bernacki, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75621?usp=email ) Change subject: mainboard/google: move tpm_tis to AMD common code ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/gpio/tpm_tis.c: https://review.coreboot.org/c/coreboot/+/75621/comment/dad66ec2_616c3342 : PS1, Line 11: if (CONFIG(BOARD_GOOGLE_NIPPERKIN) && board_id() == 1) > I think it cannot be done this way. CONFIG_TPM_GOOGLE is needed not only for tmp_tis.c file. […] Ah, so add a new Kconfig (DEFAULT_TPM_TIS_IRQ_STATUS) that is set to y when `CONFIG_TPM_GOOGLE`, but have nipperkin disable it. -- To view, visit https://review.coreboot.org/c/coreboot/+/75621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8 Gerrit-Change-Number: 75621 Gerrit-PatchSet: 1 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Jun 2023 15:23:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Grzegorz Bernacki Gerrit-MessageType: comment

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coreboot-gerrit June 2023