coreboot-gerrit June 2023

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[S] Change in coreboot[master]: soc/amd/common/acpi/pci_root: introduce ROOT_BRIDGE macro
by Matt DeVillier (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75568?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/amd/common/acpi/pci_root: introduce ROOT_BRIDGE macro ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75568/comment/5991ac46_846e4c63 : PS3, Line 11: but also allows nit: use 'as well as' ? 'but also' not typically used without preceding 'not only' https://review.coreboot.org/c/coreboot/+/75568/comment/d1ad8ffb_879d61ba : PS3, Line 12: bride bridge -- To view, visit https://review.coreboot.org/c/coreboot/+/75568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f20d694bc86da3c3c9c00fb10eecdaed1f666a8 Gerrit-Change-Number: 75568 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Jun 2023 17:38:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/acpi: move acpi_fill_root_complex_tom to Stoneyridge
by Felix Held (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75564?usp=email ) Change subject: soc/amd/common/acpi: move acpi_fill_root_complex_tom to Stoneyridge ...................................................................... Patch Set 5: (1 comment) File src/soc/amd/stoneyridge/northbridge.c: https://review.coreboot.org/c/coreboot/+/75564/comment/6e9a2b63_ece2509b : PS5, Line 171: acpi_fill_root_complex_tom > What would it take to kill this off? i'm planning to eventually get rid of that for stoneyrige too, but i didn't want to start that right now, since i'm current already more than busy and behind schedule. this requires slightly refactoring the common data fabric domain code to split it into the DF register specific and the non DF-specific part and implement the corresponding code for the registers on stoney. i started some of the work that prepares this, but i need to get some other things done before i'll finish that. the multi domain support is a bit higher on my priority list compared to stoneyridge -- To view, visit https://review.coreboot.org/c/coreboot/+/75564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9091360d6a82183092ef75417ad652523babe075 Gerrit-Change-Number: 75564 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 06 Jun 2023 17:38:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/common/block/cpu/noncar/cpu: add missing types.h include
by Fred Reitberger (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Felix Held, Jason Glenesk, Matt DeVillier. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75622?usp=email ) Change subject: soc/amd/common/block/cpu/noncar/cpu: add missing types.h include ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75622?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I875e3bb096b56bbea862c9ad0e3e14e025e3298b Gerrit-Change-Number: 75622 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Jun 2023 17:38:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common/crashlog: Add support for IOE die
by Martin L Roth (Code Review) 06 Jun '23

06 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75475?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/common/crashlog: Add support for IOE die ...................................................................... soc/intel/common/crashlog: Add support for IOE die Intel Meteor Lake SOC has a separate I/O Expander (IOE) die. SRAM from this IOE die contains crashlog records for the IPs of the IOE die. This patch adds functions with empty implementation using __weak attribute for IOE die related crashlog, changes common data structures while maintaining backwards compatibility, and support for filling IOE crashlog records, guarded by SOC_INTEL_IOE_DIE_SUPPORT config and makes cl_get_pmc_sram_data function as weak because it needs SOC specific implementation. Bug=b:262501347 TEST=Able to build. With Meteor Lake SOC related patch, able to capture and decode crashlog Change-Id: Id90cf0095258c4f7003e4c5f2564bb763e687b75 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75475 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/soc/intel/common/Kconfig.common M src/soc/intel/common/block/acpi/acpi_bert.c M src/soc/intel/common/block/crashlog/crashlog.c M src/soc/intel/common/block/include/intelblocks/crashlog.h 5 files changed, 108 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index 4162d84..5080812 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -39,6 +39,7 @@ #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_MRCDATA 0x4d524344 #define CBMEM_ID_PMC_CRASHLOG 0x504d435f +#define CBMEM_ID_IOE_CRASHLOG 0x494f455f #define CBMEM_ID_VAR_MRCDATA 0x4d524345 #define CBMEM_ID_MTC 0xcb31d31c #define CBMEM_ID_NONE 0x00000000 diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common index 29d1c7c..ed6068d 100644 --- a/src/soc/intel/common/Kconfig.common +++ b/src/soc/intel/common/Kconfig.common @@ -149,4 +149,9 @@ This will result in a BERT table being populated containing a PMC crashlog record on every boot. +config SOC_INTEL_IOE_DIE_SUPPORT + def_bool n + help + Enable this config if the SOC support IOE DIE. + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/block/acpi/acpi_bert.c b/src/soc/intel/common/block/acpi/acpi_bert.c index 16df60a..37309de 100644 --- a/src/soc/intel/common/block/acpi/acpi_bert.c +++ b/src/soc/intel/common/block/acpi/acpi_bert.c @@ -87,6 +87,29 @@ cl_fill_pmc_records(cl_data); } + if (CONFIG(SOC_INTEL_IOE_DIE_SUPPORT)) { + size_t ioe_record_size = cl_get_ioe_record_size(); + if (ioe_record_size) { + /* Allocate new FW ERR structure in case IOE crashlog is present */ + if (ioe_record_size && !bert_append_fw_err(status)) { + printk(BIOS_ERR, "Crashlog IOE entry would " + "exceed available region\n"); + return CB_ERR; + } + + cl_data = new_cper_fw_error_crashlog(status, ioe_record_size); + if (!cl_data) { + printk(BIOS_ERR, "Crashlog IOE entry(size %zu) " + "would exceed available region\n", + ioe_record_size); + return CB_ERR; + } + printk(BIOS_DEBUG, "cl_data %p, ioe_record_size %zu\n", + cl_data, ioe_record_size); + cl_fill_ioe_records(cl_data); + } + } + *length = status->data_length + gesb_header_size; *region = (void *)status; diff --git a/src/soc/intel/common/block/crashlog/crashlog.c b/src/soc/intel/common/block/crashlog/crashlog.c index 4b72599..5b098bb 100644 --- a/src/soc/intel/common/block/crashlog/crashlog.c +++ b/src/soc/intel/common/block/crashlog/crashlog.c @@ -23,6 +23,11 @@ return 0; } +int __weak cl_get_ioe_record_size(void) +{ + return 0; +} + u32 __weak cl_get_cpu_tmp_bar(void) { return 0; @@ -43,6 +48,11 @@ return false; } +bool __weak cl_ioe_sram_has_mmio_access(void) +{ + return false; +} + bool __weak cpu_crashlog_support(void) { return false; @@ -63,12 +73,19 @@ return false; } +bool __weak cl_ioe_data_present(void) +{ + return false; +} + __weak void reset_discovery_buffers(void) {} __weak void update_new_pmc_crashlog_size(u32 *pmc_crash_size) {} __weak void update_new_cpu_crashlog_size(u32 *cpu_crash_size) {} +__weak void update_new_ioe_crashlog_size(u32 *ioe_crash_size) {} + pmc_ipc_discovery_buf_t __weak cl_get_pmc_discovery_buf(void) { pmc_ipc_discovery_buf_t discov_buf; @@ -303,7 +320,7 @@ return true; } -void cl_get_pmc_sram_data(void) +void __weak cl_get_pmc_sram_data(void) { u32 *dest = NULL; u32 tmp_bar_addr = cl_get_cpu_tmp_bar(); @@ -518,3 +535,25 @@ return true; } + +bool cl_fill_ioe_records(void *cl_record) +{ + void *cl_src_addr = NULL; + + u32 m_ioe_crashLog_size = cl_get_ioe_record_size(); + + if (!cl_ioe_data_present() || m_ioe_crashLog_size == 0) { + printk(BIOS_DEBUG, "IOE crashLog not present, skipping.\n"); + return false; + } + + printk(BIOS_DEBUG, "IOE PMC crash data collection.\n"); + cl_src_addr = cbmem_find(CBMEM_ID_IOE_CRASHLOG); + if (!cl_src_addr) { + printk(BIOS_DEBUG, "IOE crash data, CBMEM not found\n"); + return false; + } + memcpy(cl_record, cl_src_addr, m_ioe_crashLog_size); + + return true; +} diff --git a/src/soc/intel/common/block/include/intelblocks/crashlog.h b/src/soc/intel/common/block/include/intelblocks/crashlog.h index cf9ddad..91e8edd 100644 --- a/src/soc/intel/common/block/include/intelblocks/crashlog.h +++ b/src/soc/intel/common/block/include/intelblocks/crashlog.h @@ -25,11 +25,16 @@ #define INVALID_CRASHLOG_RECORD 0xdeadbeef +/* Tag field definitions */ +#define CRASHLOG_DESCRIPTOR_TABLE_TAG_SOC 0x0 +#define CRASHLOG_DESCRIPTOR_TABLE_TAG_IOE 0x1 + /* PMC crashlog discovery structs */ typedef union { struct { - u16 offset; - u16 size; + u16 offset :16; + u16 size :13; + u16 assign_tag :3; } bits; u32 data; } __packed pmc_crashlog_discov_region_t; @@ -46,12 +51,34 @@ u32 discov_mechanism :2; u32 size :12; u32 base_offset :16; /* Start offset of CrashLog in PMC SSRAM */ - u32 rsv :16; - u32 desc_tabl_offset :16; /* start offset of descriptor table */ + u32 rsvd :16; + u32 desc_tabl_offset :16; /* Start offset of descriptor table */ } bits; - u64 val_64_bits; -} __packed pmc_ipc_discovery_buf_t; + u64 val_64_bits; + /* Converged Capability and Status - PMC */ + struct { + /* Capability */ + u32 supported :1; /* CrashLog feature availability bit */ + u32 dis :1; /* CrashLog Disable bit */ + u32 discov_mechanism :2; /* CrashLog discovery mechanism */ + u32 manu_trig_cmd :1; /* Manuel trigger command */ + u32 clear :1; /* Clear Command */ + u32 all_reset :1; /* Trigger on all reset command */ + u32 re_arm :1; /* Re-arm command */ + u32 glb_rst_trig_mask_sup:1; /* Global reset trigger mask supported */ + u32 rsvd :18; /* Pch Specific reserved */ + /* Status */ + u32 glb_rst_trig_mask_sts :1; /* Global reset trigger mask status */ + u32 crashLog_req :1; /* CrashLog requestor flow */ + u32 trig_armed_sts :1; /* Trigger armed status */ + u32 trig_all_rst :1; /* Trigger on all resets status */ + u32 crash_dis_sts :1; /* Crash log disabled status */ + u32 pch_rsvd :16; /* Pch Specific reserved */ + u32 desc_tabl_offset :16; /* Descriptor Table offset */ + } conv_bits64; + u64 conv_val_64_bits; +} __packed pmc_ipc_discovery_buf_t; /* CPU/TELEMETRY crashlog discovery structs */ @@ -117,8 +144,7 @@ typedef union { struct { u32 offset :32; - u32 size :16; - u32 reserved :16; + u32 size :32; } fields; u64 data; } __packed cpu_crashlog_buffer_info_t; @@ -132,20 +158,24 @@ int cl_get_cpu_record_size(void); int cl_get_pmc_record_size(void); +int cl_get_ioe_record_size(void); u32 cl_get_cpu_bar_addr(void); u32 cl_get_cpu_tmp_bar(void); u32 cl_get_cpu_mb_int_addr(void); int cl_get_total_data_size(void); bool cl_pmc_sram_has_mmio_access(void); +bool cl_ioe_sram_has_mmio_access(void); bool cpu_crashlog_support(void); bool pmc_crashlog_support(void); bool cl_cpu_data_present(void); bool cl_pmc_data_present(void); +bool cl_ioe_data_present(void); void cl_get_cpu_sram_data(void); void cl_get_pmc_sram_data(void); void reset_discovery_buffers(void); void update_new_pmc_crashlog_size(u32 *pmc_crash_size); void update_new_cpu_crashlog_size(u32 *cpu_crash_size); +void update_new_ioe_crashlog_size(u32 *pmc_crash_size); pmc_ipc_discovery_buf_t cl_get_pmc_discovery_buf(void); pmc_crashlog_desc_table_t cl_get_pmc_descriptor_table(void); cpu_crashlog_discovery_table_t cl_get_cpu_discovery_table(void); @@ -170,6 +200,7 @@ void collect_pmc_and_cpu_crashlog_from_srams(void); bool cl_fill_cpu_records(void *cl_record); bool cl_fill_pmc_records(void *cl_record); +bool cl_fill_ioe_records(void *cl_record); static const EFI_GUID FW_ERR_SECTION_GUID = { 0x81212a96, 0x09ed, 0x4996, -- To view, visit https://review.coreboot.org/c/coreboot/+/75475?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id90cf0095258c4f7003e4c5f2564bb763e687b75 Gerrit-Change-Number: 75475 Gerrit-PatchSet: 7 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/common/crashlog: Add support for IOE die
by Martin L Roth (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Paul Menzel, Pratikkumar V Prajapati. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75475?usp=email ) Change subject: soc/intel/common/crashlog: Add support for IOE die ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75475/comment/ef028c9c_261a2bd4 : PS4, Line 7: IOE die > I/O Expander Thanks. File src/soc/intel/common/block/include/intelblocks/crashlog.h: https://review.coreboot.org/c/coreboot/+/75475/comment/6223f782_ee622ba6 : PS4, Line 35: :16 > Just for consistency with other code. removing or keeping it won't matter technically. Sounds good. -- To view, visit https://review.coreboot.org/c/coreboot/+/75475?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id90cf0095258c4f7003e4c5f2564bb763e687b75 Gerrit-Change-Number: 75475 Gerrit-PatchSet: 6 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Tue, 06 Jun 2023 17:34:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/picasso/chip: use common data fabric domain resource code
by Felix Held (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Nico Huber. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74712?usp=email ) Change subject: soc/amd/picasso/chip: use common data fabric domain resource code ...................................................................... Patch Set 19: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74712/comment/ed87a79f_43a89ff6 : PS19, Line 107: reboot > They do a lot more hibernation these days to hide their slow boot times. yep. i have a half finished local patch that adds that info to the docs, but it'll probably take a while until i get that one cleaned up and ready for push and review. when debugging something else smoe months ago, this was why windows just didn't do anything when a bert table was generated, so i sort-of shelved that effort... -- To view, visit https://review.coreboot.org/c/coreboot/+/74712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia24930ec2a9962dd15e874e9defea441cffae9f2 Gerrit-Change-Number: 74712 Gerrit-PatchSet: 19 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 06 Jun 2023 17:32:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/stoneyridge/northbridge: reserve PCI config IO ports
by Felix Held (Code Review) 06 Jun '23

06 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75619?usp=email ) Change subject: soc/amd/stoneyridge/northbridge: reserve PCI config IO ports ...................................................................... soc/amd/stoneyridge/northbridge: reserve PCI config IO ports This makes sure that the resource allocator won't use those ports for anything else. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I014ffe3ee94ec153e91113f9a17e89f24ca040b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75619 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Raul Rangel: Looks good to me, approved build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 75fdfa4..452a7bb 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -334,6 +334,8 @@ pci_domain_read_resources(dev); + fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); + /* 0x0 -> 0x9ffff */ ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); -- To view, visit https://review.coreboot.org/c/coreboot/+/75619?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I014ffe3ee94ec153e91113f9a17e89f24ca040b3 Gerrit-Change-Number: 75619 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/*/root_complex: reserve PCI config IO ports
by Felix Held (Code Review) 06 Jun '23

06 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75556?usp=email ) Change subject: soc/amd/*/root_complex: reserve PCI config IO ports ...................................................................... soc/amd/*/root_complex: reserve PCI config IO ports This makes sure that the resource allocator won't use those ports for anything else. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie42260902ee2b383dd5867ac813cae029f706f2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75556 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/root_complex.c 5 files changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 6bef915..a4134ef 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -115,6 +115,8 @@ /* The root complex has no PCI BARs implemented, so there's no need to call pci_dev_read_resources for it */ + fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); + /* 0x0 - 0x9ffff */ ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index a8b54e2..9cb758a 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -130,6 +130,8 @@ /* The root complex has no PCI BARs implemented, so there's no need to call pci_dev_read_resources for it */ + fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); + /* 0x0 - 0x9ffff */ ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 53a245b..11f111f 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -158,6 +158,8 @@ /* The root complex has no PCI BARs implemented, so there's no need to call pci_dev_read_resources for it */ + fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); + /* 0x0 - 0x9ffff */ ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index 83fb047..3c754c6 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -130,6 +130,8 @@ /* The root complex has no PCI BARs implemented, so there's no need to call pci_dev_read_resources for it */ + fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); + /* 0x0 - 0x9ffff */ ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 5ea8b79..65021a3 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -115,6 +115,8 @@ /* The root complex has no PCI BARs implemented, so there's no need to call pci_dev_read_resources for it */ + fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); + /* 0x0 - 0x9ffff */ ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); -- To view, visit https://review.coreboot.org/c/coreboot/+/75556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie42260902ee2b383dd5867ac813cae029f706f2d Gerrit-Change-Number: 75556 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: {cpu, security}: Stitch multiple microcodes per CPUID into CBFS
by Subrata Banik (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Arthur Heymans, Himanshu Sahdev, Julius Werner, Lean Sheng Tan, Rizwan Qureshi, Tarun Tuli, Yu-Ping Wu. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75357?usp=email ) Change subject: {cpu, security}: Stitch multiple microcodes per CPUID into CBFS ...................................................................... Patch Set 14: (1 comment) File src/cpu/Makefile.inc: https://review.coreboot.org/c/coreboot/+/75357/comment/325231f6_ca954031 : PS10, Line 74: microcode-params := $(shell find "$(microcode-params-dir)" -type f | sed -e 's/.*\///') > > > > > > > On lighter note, ~10ms is still a big number, we are looking to optimize 2-3ms even. :P > > > > > > > > > > > > yeah on Chromebook every ms counts, I think this is also a very distinct differentiator of having coreboot instead of edk2 on Laptops ;) > > > > > > > > > > @Arthur, as i have moved the FIT microcode entry here for RO CBFS. should we need to add support for Top Swap 2nd FIT like https://review.coreboot.org/c/coreboot/+/75357/14/src/cpu/intel/fit/Makefil… ? > > > > > > > > fixing typo > > > > > > > > "don't we need to add support for Top Swap 2nd FIT as well like it had exited in other makefile https://review.coreboot.org/c/coreboot/+/75357/14/src/cpu/intel/fit/Makefil… ?" > > > > > > ping to get attention on the open question. > > > > Hmm the topswap FIT points to a separate FMAP region iirc which has only once MCU in there that the RW-A/B writes to. I believe it should be unaffected. > > okay, so we don't need to port those changes here under newly added Kconfig. @Arthur, wondering if you had chance to work on the proposed tooling for parsing the ucode blob and concluding the CPUID ? (which we can reuse while packing the respective ucode) -- To view, visit https://review.coreboot.org/c/coreboot/+/75357?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7db73335ffa25399869cfb0d59129ee118f1012 Gerrit-Change-Number: 75357 Gerrit-PatchSet: 14 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 06 Jun 2023 17:13:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/picasso/root_complex: reserve IOMMU MMIO area
by Raul Rangel (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75611?usp=email ) Change subject: soc/amd/picasso/root_complex: reserve IOMMU MMIO area ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/picasso/root_complex.c: https://review.coreboot.org/c/coreboot/+/75611/comment/36bf7139_4d178c6a : PS3, Line 151: 0xfd00000000 We don't have any #defines for this address? -- To view, visit https://review.coreboot.org/c/coreboot/+/75611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a8150873cb019ca1d903ed269e18d6f9fabb871 Gerrit-Change-Number: 75611 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Jun 2023 16:58:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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