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Change subject: mb/google/rex/var/rex0: add HID over SPI ACPI driver
......................................................................
Patch Set 12:
(1 comment)
File src/mainboard/google/rex/variants/rex0/include/variant/acpi/hid_spi_elan.asl:
https://review.coreboot.org/c/coreboot/+/74885/comment/14356947_e203e1db :
PS12, Line 13: elan7b18uh
should be change the name ?
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Change subject: soc/intel/common: Make get_ramtop_addr non static
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75624/comment/8e5c0298_794f8b00 :
PS1, Line 10: it.
> Fits on line above.
Done
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Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75624?usp=email
to look at the new patch set (#2).
Change subject: soc/intel/common: Make get_ramtop_addr non static
......................................................................
soc/intel/common: Make get_ramtop_addr non static
Make get_ramtop_addr not static to allow other code to use it.
Bug=b:276120526
TEST=Able to build rex
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
Change-Id: I8ef8a65b93645f25ca5e887342b18679d65e74b4
---
M src/soc/intel/common/basecode/include/intelbasecode/ramtop.h
M src/soc/intel/common/basecode/ramtop/ramtop.c
2 files changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/75624/2
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Change subject: drivers/usb/pci_xhci: Add two xhci DID for phoenix
......................................................................
Patch Set 2:
(1 comment)
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/75659/comment/5499bcd7_a960931e :
PS1, Line 604: PCI_DID_AMD_FAM19H_MODEL70H_XHCI1
> I'm not sure, but let's not worry about those as a part of this issue.
Please keep the bug open and add a comment in the bug regarding the USB4 XHCI controllers. That way we don't forget about it.
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Change subject: soc/intel/meteorlake: Add support for crashlog
......................................................................
Patch Set 23:
(1 comment)
File src/soc/intel/meteorlake/crashlog.c:
https://review.coreboot.org/c/coreboot/+/74769/comment/13c448c3_4ec59b02 :
PS22, Line 63: dev
> what is `dev`?
Oh ya, sorry. messed up with my older branch. Updated now.
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Hello Kane Chen, Kapil Porwal, Subrata Banik, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/meteorlake: Add support for crashlog
......................................................................
soc/intel/meteorlake: Add support for crashlog
Capture crashlog records from CPU PUNIT SRAM, SOC PMC SRAM and,
IOE SRAM. Crashlog records for IOE SRAM is discovered by
parsing SOC PMC SRAM records.
Bug=b:262501347
TEST=Able to trigger Crashlog, BERT table gets generated and decodes
as expected.
Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
---
M src/soc/intel/meteorlake/Makefile.inc
A src/soc/intel/meteorlake/crashlog.c
A src/soc/intel/meteorlake/include/soc/crashlog.h
M src/soc/intel/meteorlake/include/soc/pci_devs.h
4 files changed, 528 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/74769/23
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Change subject: soc/amd/picasso/root_complex: reserve IOMMU MMIO area
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/picasso/root_complex.c:
https://review.coreboot.org/c/coreboot/+/75611/comment/7558499c_36b8dd07 :
PS3, Line 151: 0xfd00000000
> We don't have any #defines for this address?
i'll push an update that has defines for this and adds the reservation to all socs. didn't intend to push this one yesterday evening, since i'm not done with it yet
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Change subject: drivers/usb/pci_xhci: Add two xhci DID for phoenix
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/75659/comment/bed2ea07_dc4cc7db :
PS1, Line 604: PCI_DID_AMD_FAM19H_MODEL70H_XHCI1
> 15C0 and 15C1 is USB4 I don't know where should I add?
I'm not sure, but let's not worry about those as a part of this issue.
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Change subject: soc/amd/cezanne/acpi: use ROOT_BRIDGE macro
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/cezanne/acpi/soc.asl:
https://review.coreboot.org/c/coreboot/+/75592/comment/dec5f117_78b18232 :
PS3, Line 19: #include <soc/amd/common/acpi/pci_root.asl>
> Maybe move this up as a global include since its only adding a macro and not any nodes.
good point. i'll probably wait with pushing an updated patch until the patches before this one are submitted though to not rebase the whole patc train again
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Change subject: lenovo/x230: introduce FHD variant
......................................................................
Patch Set 22:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/28950/comment/92435b48_4d82b663 :
PS22, Line 18: brightness controls to work out of the box.
> This seems misleading. Yes, it "allows" things to work OOB. But it […]
I have bought another type of kit off aliexpress where instead of tapping into the original screen interface and "proxying" the brightness values to the eDP panel, a USB HID device is exposed into the system.
But what do you understand under "firmware modifications". What firmware do you have in mind? Isn't coreboot itself being the firmware in this case? Ir are you referring to vbt?
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