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Change subject: mb/google/myst: Enable USB WWAN
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75660/comment/5862337b_03879361 :
PS3, Line 13: can be detect
> … can be detected … or just … is detected by Linux kernel.
Done
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Hello Jon Murphy, Karthik Ramasubramanian, Paul Menzel, Tim Van Patten, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/myst: Enable USB WWAN
......................................................................
mb/google/myst: Enable USB WWAN
Add usb wwan device tree entry. Also set wwan_rst to high due to
HW design active high.
BUG=b:285792436
TEST=check FM101 is detected by Linux kernel.
Bus 002 Device 002: ID 2cb7:01a2 Fibocom Wireless Inc.
Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Change-Id: I0aa60cb284d4b7f99e16643a92ee58467a355026
---
M src/mainboard/google/myst/variants/baseboard/devicetree.cb
M src/mainboard/google/myst/variants/baseboard/gpio.c
2 files changed, 20 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/75660/4
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Change subject: mb/google/myst: Enable FPMCU on UART
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75629/comment/d36d0212_2007dfec :
PS2, Line 9: FPMCU
Maybe write out fingerprint …?
https://review.coreboot.org/c/coreboot/+/75629/comment/5753e981_f4de8163 :
PS2, Line 9: per HW request
requirement?
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Change subject: mb/google/myst: Enable USB WWAN
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75660/comment/dba69129_09cb3996 :
PS3, Line 13: can be detect
… can be detected … or just … is detected by Linux kernel.
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Change subject: drivers/usb/pci_xhci: Add xhci DID for phoenix
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75659/comment/ead17455_0a2f2da0 :
PS1, Line 7: Add
Add two …
https://review.coreboot.org/c/coreboot/+/75659/comment/089c349f_eb48cbd6 :
PS1, Line 9: Add xhci DID for phoenix to get xhci SSDT.
Maybe:
> Add Phoenix xHCI device codes 0x15b9 and 0x15a0 for xHCI SSDT.
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Change subject: src/mainboard: Add Inventec transfomers setting
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75598/comment/42d22942_bf8a3eb1 :
PS2, Line 13: 1Gbase-T
Please add a space after 1.
Patchset:
PS2:
Thank you for addressing some of the comments. If you addressed a comment, you can click on *DONE* or *REPLY* and check the *Resolved* check box, if you think you addressed it.
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Change subject: mb/google/nissa: Configure the external V1p05/Vnn/VnnSx rails for joxer
......................................................................
Patch Set 1:
This change is ready for review.
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Change subject: [WIP] soc/intel/alderlake: Allow using the microcode blob from the repo
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
This also needs the file names in the `Makefile.inc` cf. CB:56862
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Change subject: soc/intel/xeon_sp/spr: Add RMT config
......................................................................
soc/intel/xeon_sp/spr: Add RMT config
This commit adds a configuration option to enable RMT in the coreboot
build for the Intel Xeon SP SPR platform.
Signed-off-by: Naresh Solanki <Naresh.Solanki(a)9elements.com>
Change-Id: I9b9276116c22cfbbec132d7a1b0026a52a51398a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75416
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---
M src/soc/intel/xeon_sp/spr/Kconfig
M src/soc/intel/xeon_sp/spr/romstage.c
2 files changed, 13 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Lean Sheng Tan: Looks good to me, approved
Felix Singer: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 308ec2d..f666ab5 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -182,4 +182,10 @@
ASPM. This option is intended for debugging and validation and
should normally be disabled.
+config ENABLE_RMT
+ bool "Enable RMT"
+ default n
+ help
+ Enable Rank Margining Tool. This option is intended for debugging and
+ validation and should normally be disabled.
endif
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index 8f4e98e..fef4d94 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -217,6 +217,13 @@
mupd->FspmConfig.KtiLinkL1En = 0;
mupd->FspmConfig.KtiLinkL0pEn = 0;
}
+
+ if (CONFIG(ENABLE_RMT)) {
+ printk(BIOS_INFO, "RMT Enabled.\n");
+ mupd->FspmConfig.EnableRMT = 0x1;
+ /* Set FSP debug message to Max for RMT logs */
+ mupd->FspmConfig.serialDebugMsgLvl = 0x3;
+ }
}
static uint8_t get_error_correction_type(const uint8_t RasModesEnabled)
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