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Change subject: mainboard/google: move tpm_tis to AMD common code
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/gpio/tpm_tis.c:
https://review.coreboot.org/c/…
[View More]coreboot/+/75621/comment/43b4f242_7ed75ea1 :
PS1, Line 11: if (CONFIG(BOARD_GOOGLE_NIPPERKIN) && board_id() == 1)
> We don't want hacks like this in common code. […]
I think it cannot be done this way. CONFIG_TPM_GOOGLE is needed not only for tmp_tis.c file. Let me think about other way to fix it.
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Change subject: mb/google/rex/variants/ovis: Add GPIO configuration
...............................…
[View More].......................................
mb/google/rex/variants/ovis: Add GPIO configuration
Based on Platform Mapping Document for Ovis (go/ovis_mapping_doc)
state for June 6, 2023 (Rev 0.3)
BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis
Change-Id: Iae3ca243a245928e8ec3d48877cf578843922fc7
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
---
M src/mainboard/google/rex/variants/ovis/gpio.c
1 file changed, 418 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/75502/7
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Change subject: mb/intel/adlrvp_rpl: Add initial code for adlrvp_rpl variant
......................................................................
mb/intel/adlrvp_rpl:…
[View More] Add initial code for adlrvp_rpl variant
This patch adds the initial code for adlrvp_rpl variant board
which includes
1. Add overridetree.cb to corresponding variant directory
2. Update mainboard name in Kconfig and Kconfig.name
3. Add config option to select corresponding overridetree.cb
BUG=b:286030718
BRANCH=firmware-brya-14505.B
TEST=Able to build with the patch and boot the adlrvp_rpl platform
to ChromeOS on Windows SKU.
Signed-off-by: Harsha B R <harsha.b.r(a)intel.com>
Change-Id: Ifb95ff705189863d23894769ff450f9528e73b14
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/Kconfig.name
A src/mainboard/intel/adlrvp/variants/adlrvp_rpl/overridetree.cb
3 files changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/73962/5
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Change subject: mb/intel/adlrvp_rpl: Add initial code for adlrvp_rpl variant
......................................................................
Patch Set 4:
This change is ready for review.
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Change subject: mb/google/myst: Enable fingerprint on UART
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75629/comment/ac6330d2_e8a9bed7 :
PS2, Line 9: FPMCU
> Maybe write …
[View More]out fingerprint …?
Done
https://review.coreboot.org/c/coreboot/+/75629/comment/48e48133_fc4de789 :
PS2, Line 9: per HW request
> requirement?
Done
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Change subject: mb/google/myst: Enable fingerprint on UART
......................................................................
mb/google/myst: Enable fingerprint …
[View More]on UART
Add fingerprint into device tree. Also set RST to low per HW
requirement.
BUG=b:285799911
TEST=check ectool --name=cros_fp version.
RO version: bloonchipper_v2.0.5938-197506c1
RO cros fwid: CROS_FWID_MISSING
RW version: bloonchipper_v2.0.14348-e5fb0b9
RW cros fwid: bloonchipper_14931.0.0
Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Change-Id: I09819037b80e55edeb56faef9e27fe0753748efc
---
M src/mainboard/google/myst/Kconfig
M src/mainboard/google/myst/variants/baseboard/gpio.c
M src/mainboard/google/myst/variants/myst/overridetree.cb
3 files changed, 20 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/75629/3
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Change subject: drivers/usb/pci_xhci: Add two xhci DID for phoenix
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75659/comment/53d69d3e_88e2fe77 :
PS1, Line 7: …
[View More]Add
> Add two …
Done
https://review.coreboot.org/c/coreboot/+/75659/comment/6d21b4e5_5fa92e0b :
PS1, Line 9: Add xhci DID for phoenix to get xhci SSDT.
> Maybe: […]
Done
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Change subject: drivers/usb/pci_xhci: Add two xhci DID for phoenix
...............................................................…
[View More].......
drivers/usb/pci_xhci: Add two xhci DID for phoenix
Add Phoenix xHCI device codes 0x15b9 and 0x15a0 for xHCI SSDT.
BUG=b:285981912
TEST=check coreboot log shows below.
[INFO ] \_SB.PCI0.GP41.XHC0.RHUB.SS01: USB3 Type-A Port A0 (MLB)
Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Change-Id: Ib59874948725966b04b54def3f6de463afeda709
---
M src/drivers/usb/pci_xhci/pci_xhci.c
M src/include/device/pci_ids.h
2 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/75659/2
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