coreboot-gerrit June 2023

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[L] Change in coreboot[master]: mb/bytedance: Add 2 SPR sockets server board bd_egs
by Name of user not set (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Nill Ge, TangYiwei. niehaitao(a)bytedance.com has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75722?usp=email ) Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: +1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d Gerrit-Change-Number: 75722 Gerrit-PatchSet: 1 Gerrit-Owner: TangYiwei Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: niehaitao(a)bytedance.com Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Thu, 08 Jun 2023 08:34:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/dedede/var/dibbi: Update power limits
by ChiaLing (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Reka Norman, Ryan Lin, Zhuohao Lee. Hello Reka Norman, Ryan Lin, Zhuohao Lee, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75681?usp=email to look at the new patch set (#3). Change subject: mb/google/dedede/var/dibbi: Update power limits ...................................................................... mb/google/dedede/var/dibbi: Update power limits Add ramstage.c in Makefile.inc and update Dibbi power limit in ramstage BUG=b:281479111 TEST=emerge-dedede coreboot and check psys and PLx value on DUT Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com> Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6 --- M src/mainboard/google/dedede/variants/dibbi/Makefile.inc A src/mainboard/google/dedede/variants/dibbi/ramstage.c 2 files changed, 73 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/75681/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/75681?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6 Gerrit-Change-Number: 75681 Gerrit-PatchSet: 3 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: include/cpu/x86/lapic.h: Add constraint for SMM
by Ziang Wang (Code Review) 08 Jun '23

08 Jun '23

Ziang Wang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/74054?usp=email ) Change subject: include/cpu/x86/lapic.h: Add constraint for SMM ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/74054?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib96f371681b6f79f02a115126f7bd9b692293ece Gerrit-Change-Number: 74054 Gerrit-PatchSet: 2 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-CC: Nill Ge <geshijian(a)bytedance.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: TangYiwei Gerrit-MessageType: abandon

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[L] Change in coreboot[master]: mb/bytedance: Add 2 SPR sockets server board bd_egs
by TangYiwei (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Nill Ge, niehaitao(a)bytedance.com. Hello niehaitao(a)bytedance.com, Nill Ge, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/75722?usp=email to review the following change. Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs ...................................................................... mb/bytedance: Add 2 SPR sockets server board bd_egs Bytedance bd_egs is a dual socket MB with Intel Sapphire Rapids Scalable Processor chipset. Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d Co-authored-by: Jeff Li <lijinfeng01(a)ieisystem.com> Co-authored-by: Yuuka_Kazami <caolong01(a)inspur.com> Co-authored-by: wanghao11 <wanghao11(a)inspur.com> Co-authored-by: lanchenyu <lanchenyu(a)inspur.com> Co-authored-by: laykong <lay.kong(a)intel.com> Co-authored-by: kehong-intel <kehong.chen(a)intel.com> Co-authored-by: ziang <ziang.wang(a)intel.com> Co-authored-by: weidong <weidong.wd(a)bytedance.com> Co-authored-by: lichenchen.carl <lichenchen.carl(a)bytedance.com> Signed-off-by: Yiwei Tang <tangyiwei.2022(a)bytedance.com> Reviewed-by: Haitao Nie<niehaitao(a)bytedance.com> Reviewed-by: Shijian Ge<geshijian(a)bytedance.com> --- A src/mainboard/bytedance/Kconfig A src/mainboard/bytedance/Kconfig.name A src/mainboard/bytedance/bd_egs/Kconfig A src/mainboard/bytedance/bd_egs/Kconfig.name A src/mainboard/bytedance/bd_egs/Makefile.inc A src/mainboard/bytedance/bd_egs/acpi/platform.asl A src/mainboard/bytedance/bd_egs/board.fmd A src/mainboard/bytedance/bd_egs/board_info.txt A src/mainboard/bytedance/bd_egs/bootblock.c A src/mainboard/bytedance/bd_egs/devicetree.cb A src/mainboard/bytedance/bd_egs/dsdt.asl A src/mainboard/bytedance/bd_egs/gpio.c A src/mainboard/bytedance/bd_egs/gpio.h A src/mainboard/bytedance/bd_egs/include/sprsp_bd_iio.h A src/mainboard/bytedance/bd_egs/ramstage.c A src/mainboard/bytedance/bd_egs/romstage.c 16 files changed, 782 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/75722/1 diff --git a/src/mainboard/bytedance/Kconfig b/src/mainboard/bytedance/Kconfig new file mode 100644 index 0000000..87d38e7 --- /dev/null +++ b/src/mainboard/bytedance/Kconfig @@ -0,0 +1,18 @@ +if VENDOR_BYTEDANCE + +choice + prompt "Mainboard model" + +source "src/mainboard/bytedance/*/Kconfig.name" + +endchoice + +source "src/mainboard/bytedance/*/Kconfig" + +config MAINBOARD_VENDOR + default "ByteDance" + +config MAINBOARD_FAMILY + default "Family" + +endif # VENDOR_BYTEDANCE diff --git a/src/mainboard/bytedance/Kconfig.name b/src/mainboard/bytedance/Kconfig.name new file mode 100644 index 0000000..e6d6a7b --- /dev/null +++ b/src/mainboard/bytedance/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_BYTEDANCE + bool "ByteDance" diff --git a/src/mainboard/bytedance/bd_egs/Kconfig b/src/mainboard/bytedance/bd_egs/Kconfig new file mode 100644 index 0000000..ce815ba --- /dev/null +++ b/src/mainboard/bytedance/bd_egs/Kconfig @@ -0,0 +1,36 @@ +if BOARD_BYTEDANCE_BD_EGS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select MAINBOARD_USES_FSP2_0 + select SOC_INTEL_SAPPHIRERAPIDS_SP + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + select MAINBOARD_USES_IFD_GBE_REGION + select IPMI_KCS + select MEMORY_MAPPED_TPM + select MAINBOARD_HAS_TPM2 + select INTEL_DESCRIPTOR_MODE_CAPABLE + +config MAINBOARD_DIR + string + default "bytedance/bd_egs" + +config MAINBOARD_PART_NUMBER + string + default "ByteDance Eaglestream" + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config MAX_SOCKET + int + default 2 + +config ACPI_CPU_STRING + string + default "\\_SB.C%03d" + +endif diff --git a/src/mainboard/bytedance/bd_egs/Kconfig.name b/src/mainboard/bytedance/bd_egs/Kconfig.name new file mode 100644 index 0000000..60f5f2a --- /dev/null +++ b/src/mainboard/bytedance/bd_egs/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_BYTEDANCE_BD_EGS + bool "ByteDance Eaglestream" diff --git a/src/mainboard/bytedance/bd_egs/Makefile.inc b/src/mainboard/bytedance/bd_egs/Makefile.inc new file mode 100644 index 0000000..e6e739e --- /dev/null +++ b/src/mainboard/bytedance/bd_egs/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += bootblock.c gpio.c +romstage-y += romstage.c +ramstage-y += ramstage.c gpio.c +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/bytedance/bd_egs/acpi/platform.asl b/src/mainboard/bytedance/bd_egs/acpi/platform.asl new file mode 100644 index 0000000..4853874 --- /dev/null +++ b/src/mainboard/bytedance/bd_egs/acpi/platform.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Enable ACPI _SWS methods */ +#include <soc/intel/common/acpi/acpi_wake_source.asl> +#include <southbridge/intel/common/acpi/sleepstates.asl> + +/* Port 80 POST */ +OperationRegion (DBG0, SystemIO, 0x80, 0x02) +Field (DBG0, ByteAcc, Lock, Preserve) +{ + IO80, 8, + IO81, 8 +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method (_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method (_WAK, 1) +{ + Return (Package (){ 0, 0 }) +} diff --git a/src/mainboard/bytedance/bd_egs/board.fmd b/src/mainboard/bytedance/bd_egs/board.fmd new file mode 100644 index 0000000..1a58bb1 --- /dev/null +++ b/src/mainboard/bytedance/bd_egs/board.fmd @@ -0,0 +1,13 @@ +FLASH@0xfc000000 64M { + SI_ALL@0x0 0x03000000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x2fed000 + SI_PT@0x2ff0000 0x10000 + } + RW_MRC_CACHE@0x3000000 0x18000 + FMAP 0x1000 + RW_VPD(PRESERVE) 0x4000 + RO_VPD(PRESERVE) 0x4000 + COREBOOT(CBFS) +} diff --git a/src/mainboard/bytedance/bd_egs/board_info.txt b/src/mainboard/bytedance/bd_egs/board_info.txt new file mode 100644 index 0000000..1e5c3cd --- /dev/null +++ b/src/mainboard/bytedance/bd_egs/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: ByteDance +Board name: Eaglestream +Category: eval +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/bytedance/bd_egs/bootblock.c b/src/mainboard/bytedance/bd_egs/bootblock.c new file mode 100644 index 0000000..46abbe7 --- /dev/null +++ b/src/mainboard/bytedance/bd_egs/bootblock.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> +#include <soc/gpio.h> +#include "gpio.h" + +#define ASPEED_SIO_PORT 0x2E +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 + +void bootblock_mainboard_early_init(void) +{ + /* + * Set up decoding windows on PCH over PCR. The CPU uses two of AST2600 SIO ports, + * one is connected to debug header (SUART1) and another is used as SOL (SUART2). + * For ArcherCity CRB, only SUART1 is used. + */ + uint16_t lpciod = (LPC_IOD_COMB_RANGE | LPC_IOD_COMA_RANGE); + uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMB_EN | LPC_IOE_COMA_EN); + + /* Open IO windows: 0x3f8 for com1 and 02f8 for com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod); + /* LPC I/O enable: com1 and com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe); + + /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod); + pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe); + + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + + const struct pad_config *pads; + size_t pads_num; + pads = get_gpio_table(&pads_num); + gpio_configure_pads(pads, pads_num); +} diff --git a/src/mainboard/bytedance/bd_egs/devicetree.cb b/src/mainboard/bytedance/bd_egs/devicetree.cb new file mode 100644 index 0000000..66a08a9 --- /dev/null +++ b/src/mainboard/bytedance/bd_egs/devicetree.cb @@ -0,0 +1,35 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/xeon_sp/spr + # configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs + register "turbo_ratio_limit" = "0x181819191e242424" + register "turbo_ratio_limit_cores" = "0x3836322e2a1c1a18" + + device domain 0 on + device pci 1f.0 on # Intel device 1b81: PCH eSPI controller + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "1" + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + end + end + chip drivers/ipmi # BMC KCS + device pnp ca2.0 on end + register "bmc_i2c_address" = "0x20" + register "bmc_boot_timeout" = "60" + end + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 on end + end + end + end +end diff --git a/src/mainboard/bytedance/bd_egs/dsdt.asl b/src/mainboard/bytedance/bd_egs/dsdt.asl new file mode 100644 index 0000000..2204748 --- /dev/null +++ b/src/mainboard/bytedance/bd_egs/dsdt.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + // platform ACPI tables + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + // SPR-SP ACPI tables + #include <soc/intel/xeon_sp/spr/acpi/uncore.asl> + + // LPC related entries + Scope (\_SB.PC00) + { + #include <soc/intel/xeon_sp/spr/acpi/pch.asl> + } +} diff --git a/src/mainboard/bytedance/bd_egs/gpio.c b/src/mainboard/bytedance/bd_egs/gpio.c new file mode 100644 index 0000000..6c9dcf1 --- /dev/null +++ b/src/mainboard/bytedance/bd_egs/gpio.c @@ -0,0 +1,300 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/gpio.h> + +#include "gpio.h" + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF_OWN(GPPC_A0, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPPC_A1, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPPC_A2, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPPC_A3, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPPC_A4, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPPC_A5, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPPC_A6, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPPC_A7, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPPC_A8, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPPC_A9, DN_20K, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_A10, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_A11, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPPC_A12, 0, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPPC_A13, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_A14, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPPC_A15, 1, DEEP), + PAD_CFG_GPIO_OWN(GPPC_A16, NONE, DEEP, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_A17, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_A18, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_A19, NONE, DEEP, OFF, ACPI), + + PAD_CFG_NF_OWN(GPPC_B0, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWN(GPPC_B1, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWN(GPPC_B2, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWN(GPPC_B3, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWN(GPPC_B4, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWN(GPPC_B5, NONE, DEEP, NF4, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_B6, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWN(GPPC_B7, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPPC_B8, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_B9, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_B10, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_B11, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWN(GPPC_B12, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWN(GPPC_B13, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWN(GPPC_B14, NONE, DEEP, NF4, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_B15, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_B16, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_B17, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_B18, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_B19, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_B20, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_NMI(GPPC_B21, NONE, DEEP, LEVEL, INVERT), + PAD_CFG_GPI_TRIG_OWN(GPPC_B22, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_B23, NONE, DEEP, OFF, ACPI), + + PAD_CFG_NF_OWN(GPPC_C0, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPPC_C1, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPO(GPPC_C2, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPPC_C3, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_C4, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_C5, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWN(GPPC_C6, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPPC_C7, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPPC_C8, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_C9, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_C10, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPPC_C11, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPPC_C12, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_C13, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPPC_C14, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPPC_C15, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_C16, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPPC_C17, 1, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPPC_C18, NONE, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_C19, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_C20, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_C21, NONE, DEEP, OFF, ACPI), + + PAD_CFG_NF_OWN(GPP_D0, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_D1, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_D3, 0, DEEP), + PAD_CFG_GPO(GPP_D4, 0, DEEP), + PAD_CFG_GPO(GPP_D5, 0, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWN(GPP_D8, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_D9, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWN(GPP_D11, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_D12, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_D13, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_D14, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_D15, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_D16, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_D17, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWN(GPP_D21, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, DEEP, OFF, ACPI), + + PAD_CFG_GPI_TRIG_OWN(GPP_E0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_E4, 0, DEEP), // FIXME: GpioOutDefault + PAD_CFG_GPO(GPP_E5, 0, DEEP), // FIXME: GpioOutDefault + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E8, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E9, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_E11, 0, DEEP), // FIXME: GpioOutDefault + PAD_CFG_GPI_TRIG_OWN(GPP_E12, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E13, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E14, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E15, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E18, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E19, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_E20, 0, DEEP), + PAD_CFG_GPO(GPP_E21, 0, DEEP), + PAD_CFG_GPO(GPP_E22, 0, DEEP), + PAD_CFG_GPO(GPP_E23, 0, DEEP), + + PAD_CFG_GPI_TRIG_OWN(GPPC_H0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H1, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPPC_H2, 0, DEEP), + PAD_CFG_GPO(GPPC_H3, 0, DEEP), + PAD_CFG_GPO(GPPC_H4, 0, DEEP), + PAD_CFG_GPO(GPPC_H5, 0, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPPC_H6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H7, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPPC_H8, 0, DEEP), + PAD_CFG_GPO(GPPC_H9, 0, DEEP), + PAD_CFG_GPO(GPPC_H10, 0, DEEP), + PAD_CFG_GPO(GPPC_H11, 0, DEEP), + PAD_CFG_GPO(GPPC_H12, 0, DEEP), + PAD_CFG_GPO(GPPC_H13, 0, DEEP), + PAD_CFG_GPO(GPPC_H14, 0, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPPC_H15, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H16, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H17, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H18, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H19, NONE, DEEP, OFF, ACPI), + + PAD_CFG_GPO(GPP_I0, 0, DEEP), + PAD_CFG_GPO(GPP_I1, 0, DEEP), + PAD_CFG_GPO(GPP_I2, 0, DEEP), + PAD_CFG_GPO(GPP_I3, 0, DEEP), + PAD_CFG_GPO(GPP_I4, 0, DEEP), + PAD_CFG_GPO(GPP_I5, 0, DEEP), + PAD_CFG_GPO(GPP_I6, 0, DEEP), + PAD_CFG_GPO(GPP_I7, 0, DEEP), + PAD_CFG_GPO(GPP_I8, 0, DEEP), + PAD_CFG_GPO(GPP_I9, 0, DEEP), + PAD_CFG_GPO(GPP_I10, 0, DEEP), + PAD_CFG_GPO(GPP_I11, 0, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_I12, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_I13, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_I14, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_I15, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_I16, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_I17, 0, DEEP), + PAD_CFG_GPO(GPP_I18, 0, DEEP), + PAD_CFG_GPO(GPP_I19, 0, DEEP), + PAD_CFG_GPO(GPP_I20, 0, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_I21, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_I22, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_I23, NONE, DEEP, OFF, ACPI), + + PAD_CFG_NF_OWN(GPP_J0, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_J1, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPO(GPP_J2, 0, DEEP), + PAD_CFG_NF_OWN(GPP_J3, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_J4, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_J5, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_J6, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_J7, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_J8, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPO(GPP_J9, 0, DEEP), + PAD_CFG_GPO(GPP_J10, 0, DEEP), + PAD_CFG_GPO(GPP_J11, 0, DEEP), + PAD_CFG_NF_OWN(GPP_J12, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_J13, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_J14, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_J15, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_GPO(GPP_J16, 0, DEEP), + PAD_CFG_GPO(GPP_J17, 0, DEEP), + + PAD_CFG_NF_OWN(GPP_L0, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_L1, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_L2, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_L3, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_L4, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_L5, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_L6, NONE, DEEP, OFF, DRIVER), + PAD_CFG_GPI_TRIG_OWN(GPP_L7, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_L8, 0, DEEP), + PAD_CFG_GPO(GPP_L9, 0, DEEP), + PAD_CFG_GPO(GPP_L10, 0, DEEP), + PAD_CFG_GPO(GPP_L11, 0, DEEP), + PAD_CFG_GPO(GPP_L12, 0, DEEP), + PAD_CFG_GPO(GPP_L13, 0, DEEP), + PAD_CFG_GPO(GPP_L14, 0, DEEP), + PAD_CFG_GPO(GPP_L15, 0, DEEP), + PAD_CFG_GPO(GPP_L16, 0, DEEP), + PAD_CFG_GPO(GPP_L17, 0, DEEP), + + PAD_CFG_GPI_TRIG_OWN(GPP_M0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M1, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M2, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M3, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M4, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M5, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M7, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M8, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_M9, 0, DEEP), + PAD_CFG_GPO(GPP_M10, 0, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_M11, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M12, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_M13, 0, DEEP), + PAD_CFG_GPO(GPP_M14, 0, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_M15, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M16, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M17, NONE, DEEP, OFF, ACPI), + + PAD_CFG_GPO(GPP_N0, 0, DEEP), + PAD_CFG_GPO(GPP_N1, 0, DEEP), + PAD_CFG_GPO(GPP_N2, 0, DEEP), + PAD_CFG_GPO(GPP_N3, 0, DEEP), + PAD_CFG_GPO(GPP_N4, 0, DEEP), + PAD_CFG_GPO(GPP_N5, 0, DEEP), + PAD_CFG_GPO(GPP_N6, 0, DEEP), + PAD_CFG_GPO(GPP_N7, 0, DEEP), + PAD_CFG_GPO(GPP_N8, 0, DEEP), + PAD_CFG_GPO(GPP_N9, 0, DEEP), + PAD_CFG_GPO(GPP_N10, 0, DEEP), + PAD_CFG_GPO(GPP_N11, 0, DEEP), + PAD_CFG_GPO(GPP_N12, 0, DEEP), + PAD_CFG_GPO(GPP_N13, 0, DEEP), + PAD_CFG_GPO(GPP_N14, 0, DEEP), + PAD_CFG_GPO(GPP_N15, 0, DEEP), + PAD_CFG_GPO(GPP_N16, 0, DEEP), + PAD_CFG_GPO(GPP_N17, 0, DEEP), + + PAD_CFG_GPI_TRIG_OWN(GPP_O1, NONE, PWROK, OFF, ACPI), + PAD_CFG_NF_OWN(GPP_O2, NONE, PWROK, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_O3, NONE, PWROK, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_O4, NONE, PWROK, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_O5, NONE, PWROK, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_O6, NONE, PWROK, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_O7, NONE, PWROK, OFF, ACPI), + PAD_CFG_GPO(GPP_O8, 0, PWROK), + PAD_CFG_GPO(GPP_O9, 0, PWROK), + PAD_CFG_NF_OWN(GPP_O10, NONE, PWROK, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_O11, NONE, PWROK, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_O12, NONE, PWROK, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_O13, NONE, PWROK, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_O14, NONE, PWROK, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_O15, NONE, PWROK, NF1, ACPI), + PAD_CFG_NF_OWN(GPP_O16, NONE, PWROK, NF1, ACPI), + + PAD_CFG_GPI_TRIG_OWN(GPPC_S0, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWN(GPPC_S1, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_S2, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_S3, NONE, RSMRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_S4, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_S5, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWN(GPPC_S6, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPPC_S7, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPPC_S8, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWN(GPPC_S9, NONE, DEEP, NF1, DRIVER), + PAD_CFG_GPI_TRIG_OWN(GPPC_S10, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_S11, NONE, DEEP, OFF, ACPI), +}; + +static const struct pad_config override_fsp_gpio_table[] = { + PAD_CFG_GPI_TRIG_OWN(GPPC_B10, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_B11, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWN(GPPC_B12, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWN(GPPC_B13, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWN(GPPC_B14, NONE, DEEP, NF4, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_B15, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, DEEP, OFF, ACPI), +}; + +const struct pad_config *get_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *get_override_fsp_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_fsp_gpio_table); + return override_fsp_gpio_table; +} diff --git a/src/mainboard/bytedance/bd_egs/gpio.h b/src/mainboard/bytedance/bd_egs/gpio.h new file mode 100644 index 0000000..7732c93 --- /dev/null +++ b/src/mainboard/bytedance/bd_egs/gpio.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> + +/* Native function configuration */ +#define PAD_CFG_NF_OWN(pad, pull, rst, func, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_FUNC(func) | PAD_TRIG(OFF), \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | \ + PAD_CFG_OWN_GPIO(own)) + +#define PAD_CFG_GPIO_OWN(pad, pull, rst, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(OFF), \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) + +const struct pad_config *get_gpio_table(size_t *num); + +const struct pad_config *get_override_fsp_gpio_table(size_t *num); diff --git a/src/mainboard/bytedance/bd_egs/include/sprsp_bd_iio.h b/src/mainboard/bytedance/bd_egs/include/sprsp_bd_iio.h new file mode 100644 index 0000000..62d3859 --- /dev/null +++ b/src/mainboard/bytedance/bd_egs/include/sprsp_bd_iio.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SPRSP_BD_IIO_H_ +#define _SPRSP_BD_IIO_H_ + +#include <defs_iio.h> + +/* For now only set 3 fields and hard-coded others, should be extended in the future */ +#define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp) \ + { \ + .SLOTEIP = 0, \ + .SLOTHPCAP = 0, \ + .SLOTHPSUP = 0, \ + .SLOTPIP = 0, \ + .SLOTAIP = 0, \ + .SLOTMRLSP = 0, \ + .SLOTPCP = 0, \ + .SLOTABP = 0, \ + .SLOTIMP = slotimp, \ + .SLOTSPLS = 0, \ + .SLOTSPLV = 0, \ + .SLOTPSP = slotpsp, \ + .VppEnabled = 0, \ + .VppPort = 0, \ + .VppAddress = 0, \ + .MuxAddress = 0, \ + .ChannelID = 0, \ + .PciePortEnable = 1, \ + .PEXPHIDE = pexphide, \ + .HidePEXPMenu = 0, \ + .PciePortOwnership = 0, \ + .RetimerConnectCount = 0, \ + } + +/* + * ByteDance IIO PCIe Port Table + */ +static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY bd_iio_pci_port_skt0[] = { + /* DMI port: array index 0 */ + CFG_UPD_PCIE_PORT(0, 0, 0), + /* IOU0 (PE0): array index 1 ~ 8 */ + CFG_UPD_PCIE_PORT(0, 1, 101), /* 15:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 103), /* 15:03.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 105), /* 15:05.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 107), /* 15:07.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU1 (PE1): array index 9 ~ 16 */ + CFG_UPD_PCIE_PORT(0, 1, 109), /* 26:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 111), /* 26:03.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 113), /* 26:05.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 115), /* 26:07.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU2 (PE2): array index 17 ~ 24 */ + CFG_UPD_PCIE_PORT(0, 1, 17), /* 37:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU3 (PE3): array index 25 ~ 32 */ + CFG_UPD_PCIE_PORT(0, 1, 25), /* 48:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 129), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 131), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU4 (PE4): array index 33 ~ 40 */ + CFG_UPD_PCIE_PORT(0, 1, 133), /* 59:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 135), /* 59:03.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 137), /* 59:05.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 139), /* 59:07.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* Bytedance doesn't use IOU5 ~ IOU6. */ +}; + +static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY bd_iio_pci_port_skt1[] = { + /* DMI port: array index 0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU0 (PE0): array index 1 ~ 8 */ + CFG_UPD_PCIE_PORT(0, 1, 41), /* 97:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU1 (PE1): array index 9 ~ 16 */ + CFG_UPD_PCIE_PORT(0, 1, 149), /* a7:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 151), /* a7:03.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 153), /* a7:05.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 155), /* a7:07.0 */ + CFG_UPD_PCIE_PORT(0, 0, 0), + /* IOU2 (PE2): array index 17 ~ 24 */ + CFG_UPD_PCIE_PORT(0, 1, 157), /* b7:01.0 */ //only use 1 x4. + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 1, 100), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 1, 100), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 1, 100), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU3 (PE3): array index 25 ~ 32 */ + CFG_UPD_PCIE_PORT(0, 1, 165), /* c7:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 167), /* c7:03.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 169), /* c7:05.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 171), /* c7:07.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU4 (PE4): array index 33 ~ 40 */ + CFG_UPD_PCIE_PORT(0, 1, 173), /* d7:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 175), /* d7:03.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 177), /* d7:05.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 179), /* d7:07.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* Bytedance doesn't use IOU5 ~ IOU6. */ +}; +#endif /* _SPRSP_BD_IIO_H_ */ diff --git a/src/mainboard/bytedance/bd_egs/ramstage.c b/src/mainboard/bytedance/bd_egs/ramstage.c new file mode 100644 index 0000000..3af3b35 --- /dev/null +++ b/src/mainboard/bytedance/bd_egs/ramstage.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> +#include <soc/gpio.h> + +#include "gpio.h" + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ +} + +static void mainboard_chip_init(void *chip_info) +{ + const struct pad_config *pads; + size_t pads_num; + + pads = get_gpio_table(&pads_num); + gpio_configure_pads(pads, pads_num); +} + +void mainboard_override_fsp_gpio(void) +{ + const struct pad_config *pads; + size_t pads_num; + + pads = get_override_fsp_gpio_table(&pads_num); + gpio_configure_pads(pads, pads_num); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_chip_init, +}; diff --git a/src/mainboard/bytedance/bd_egs/romstage.c b/src/mainboard/bytedance/bd_egs/romstage.c new file mode 100644 index 0000000..e010867 --- /dev/null +++ b/src/mainboard/bytedance/bd_egs/romstage.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/romstage.h> +#include <defs_cxl.h> +#include <defs_iio.h> +#include <sprsp_bd_iio.h> + +static void mainboard_config_iio(FSPM_UPD *mupd) +{ + int port; + + UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig = + (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr; + + /* Socket0: Array bd_iio_pci_port_skt0 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */ + for (port = 0; port < ARRAY_SIZE(bd_iio_pci_port_skt0); port++) { + PciePortConfig[0].SLOTIMP[port] = bd_iio_pci_port_skt0[port].SLOTIMP; + PciePortConfig[0].SLOTPSP[port] = bd_iio_pci_port_skt0[port].SLOTPSP; + PciePortConfig[0].PciePortEnable[port] = bd_iio_pci_port_skt0[port].PciePortEnable; + PciePortConfig[0].PEXPHIDE[port] = bd_iio_pci_port_skt0[port].PEXPHIDE; + PciePortConfig[0].SLOTHPCAP[port] = bd_iio_pci_port_skt0[port].SLOTHPCAP; + PciePortConfig[0].VppPort[port] = bd_iio_pci_port_skt0[port].VppPort; + PciePortConfig[0].VppAddress[port] = bd_iio_pci_port_skt0[port].VppAddress; + } + /* Socket0: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */ + for (port = ARRAY_SIZE(bd_iio_pci_port_skt0); port < MAX_IIO_PORTS_PER_SOCKET; port++) { + PciePortConfig[0].PEXPHIDE[port] = 1; + PciePortConfig[0].HidePEXPMenu[port] = 1; + } + PciePortConfig[0].ConfigIOU[0] = IIO_BIFURCATE_x4x4x4x4; + PciePortConfig[0].ConfigIOU[1] = IIO_BIFURCATE_x4x4x4x4; + PciePortConfig[0].ConfigIOU[2] = IIO_BIFURCATE_xxxxxx16; + PciePortConfig[0].ConfigIOU[3] = IIO_BIFURCATE_x4x4xxx8; + PciePortConfig[0].ConfigIOU[4] = IIO_BIFURCATE_x4x4x4x4; + + /* Socket1: Array bd_iio_pci_port_skt1 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */ + for (port = 0; port < ARRAY_SIZE(bd_iio_pci_port_skt1); port++) { + PciePortConfig[1].SLOTIMP[port] = bd_iio_pci_port_skt1[port].SLOTIMP; + PciePortConfig[1].SLOTPSP[port] = bd_iio_pci_port_skt1[port].SLOTPSP; + PciePortConfig[1].PciePortEnable[port] = bd_iio_pci_port_skt1[port].PciePortEnable; + PciePortConfig[1].PEXPHIDE[port] = bd_iio_pci_port_skt1[port].PEXPHIDE; + PciePortConfig[1].SLOTHPCAP[port] = bd_iio_pci_port_skt1[port].SLOTHPCAP; + PciePortConfig[1].VppPort[port] = bd_iio_pci_port_skt1[port].VppPort; + PciePortConfig[1].VppAddress[port] = bd_iio_pci_port_skt1[port].VppAddress; + } + /* Socket1: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */ + for (port = ARRAY_SIZE(bd_iio_pci_port_skt1); port < MAX_IIO_PORTS_PER_SOCKET; port++) { + PciePortConfig[1].PEXPHIDE[port] = 1; + PciePortConfig[1].HidePEXPMenu[port] = 1; + } + PciePortConfig[1].ConfigIOU[0] = IIO_BIFURCATE_xxxxxx16; + PciePortConfig[1].ConfigIOU[1] = IIO_BIFURCATE_x4x4x4x4; + PciePortConfig[1].ConfigIOU[2] = IIO_BIFURCATE_x4x4x4x4; + PciePortConfig[1].ConfigIOU[3] = IIO_BIFURCATE_x4x4x4x4; + PciePortConfig[1].ConfigIOU[4] = IIO_BIFURCATE_x4x4x4x4; +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + /* Disable CXL header bypass */ + mupd->FspmConfig.DfxCxlHeaderBypass = 0; + + /* Set DFX CXL security level to fully trusted */ + mupd->FspmConfig.DfxCxlSecLvl = CXL_SECURITY_FULLY_TRUSTED; + + /* Set DelayAfterPCIeLinkTraining to 2000 ms */ + mupd->FspmConfig.DelayAfterPCIeLinkTraining = 2000; + + mainboard_config_iio(mupd); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/75722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d Gerrit-Change-Number: 75722 Gerrit-PatchSet: 1 Gerrit-Owner: TangYiwei Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: niehaitao(a)bytedance.com Gerrit-Attention: niehaitao(a)bytedance.com Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: soc/intel/jasperlake: Add per-SKU power limits
by ChiaLing (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Paul Menzel, Reka Norman, Ryan Lin, Zhuohao Lee. ChiaLing has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75679?usp=email ) Change subject: soc/intel/jasperlake: Add per-SKU power limits ...................................................................... Patch Set 4: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75679/comment/aa4397a5_b9f9d8be : PS1, Line 10: devicetree. > Fits on the line above. Acknowledged https://review.coreboot.org/c/coreboot/+/75679/comment/d0602514_4fcd8a5a : PS1, Line 11: > Please document the source for these limits. It shows in PDG. https://review.coreboot.org/c/coreboot/+/75679/comment/9219b909_a9339b58 : PS1, Line 13: TEST=emerge-dedede coreboot and read correct value : on DUT register > Fits into 72 characters. Acknowledged https://review.coreboot.org/c/coreboot/+/75679/comment/450eeae1_bc92c678 : PS1, Line 15: > On what board? On Dibbi. -- To view, visit https://review.coreboot.org/c/coreboot/+/75679?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd Gerrit-Change-Number: 75679 Gerrit-PatchSet: 4 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 08:18:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Add PsysPl1 support
by ChiaLing (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Reka Norman, Ryan Lin, Zhuohao Lee. ChiaLing has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75678?usp=email ) Change subject: soc/intel/common: Add PsysPl1 support ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Fix patch relation chain at here. Sorry for the spam. -- To view, visit https://review.coreboot.org/c/coreboot/+/75678?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b2cf2c90ddef422c121e90edbe79dacb7e29320 Gerrit-Change-Number: 75678 Gerrit-PatchSet: 1 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 07:51:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/jasperlake: Add per-SKU power limits
by ChiaLing (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Reka Norman, Ryan Lin, Zhuohao Lee. ChiaLing has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75679?usp=email ) Change subject: soc/intel/jasperlake: Add per-SKU power limits ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Fix patch relation chain at here. Sorry for the spam. -- To view, visit https://review.coreboot.org/c/coreboot/+/75679?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd Gerrit-Change-Number: 75679 Gerrit-PatchSet: 4 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 07:51:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/dedede: Support variant specific power limits
by ChiaLing (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Reka Norman, Ryan Lin, Zhuohao Lee. ChiaLing has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75680?usp=email ) Change subject: mb/google/dedede: Support variant specific power limits ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Fix patch relation chain at here. Sorry for the spam. -- To view, visit https://review.coreboot.org/c/coreboot/+/75680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I583c930379233322c41027805369f81d02000ee7 Gerrit-Change-Number: 75680 Gerrit-PatchSet: 2 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 07:50:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/dedede/var/dibbi: Update power limits
by ChiaLing (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Reka Norman, Ryan Lin, Zhuohao Lee. ChiaLing has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75681?usp=email ) Change subject: mb/google/dedede/var/dibbi: Update power limits ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Fix patch relation chain at here. Sorry for the spam. -- To view, visit https://review.coreboot.org/c/coreboot/+/75681?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6 Gerrit-Change-Number: 75681 Gerrit-PatchSet: 2 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 07:50:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex/var/screebo: Enable touchscreen
by Rui Zhou (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli, zhongtian wu. Rui Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75692?usp=email ) Change subject: mb/google/rex/var/screebo: Enable touchscreen ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I think we don't need much, although it is a different touch screen, but the i2c address is not the […] Sorry, I made a mistake, it is the same screen, but the touch ic is different. -- To view, visit https://review.coreboot.org/c/coreboot/+/75692?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57d55c5f2621d6fafd53b19d12ecad20271cdbb1 Gerrit-Change-Number: 75692 Gerrit-PatchSet: 1 Gerrit-Owner: zhongtian wu <wuzhongtian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: zhongtian wu <wuzhongtian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 07:43:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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