coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[master]: mb/google/rex/variants/ovis: Add SPI configuration
by Kapil Porwal (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Jakub Czapiga, Subrata Banik, Tarun Tuli. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75577?usp=email ) Change subject: mb/google/rex/variants/ovis: Add SPI configuration ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75577?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f3fa6543a4cec8c2562196105f17fbc7831bab7 Gerrit-Change-Number: 75577 Gerrit-PatchSet: 5 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 10:06:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/dedede/var/dibbi: Update power limits
by ChiaLing (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Reka Norman, Ryan Lin, Zhuohao Lee. Hello Reka Norman, Ryan Lin, Zhuohao Lee, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75681?usp=email to look at the new patch set (#4). Change subject: mb/google/dedede/var/dibbi: Update power limits ...................................................................... mb/google/dedede/var/dibbi: Update power limits Add ramstage.c in Makefile.inc and update Dibbi power limit in ramstage BUG=b:281479111 TEST=emerge-dedede coreboot and check psys and PLx value on DUT Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com> Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6 --- M src/mainboard/google/dedede/variants/dibbi/Makefile.inc A src/mainboard/google/dedede/variants/dibbi/ramstage.c 2 files changed, 73 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/75681/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/75681?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6 Gerrit-Change-Number: 75681 Gerrit-PatchSet: 4 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG
by Harsha B R (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Bernardo Perez Priego, Jamie Ryu, Jay Patel, Kapil Porwal, Li1 Feng, Tarun Tuli, Wonkyu Kim. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75525?usp=email ) Change subject: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG ...................................................................... Patch Set 8: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/75525?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749 Gerrit-Change-Number: 75525 Gerrit-PatchSet: 8 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Jay Patel <jay2.patel(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 09:45:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/mediatek/mt8195: Fix typo for SPIM2_MI
by Yidi Lin (Code Review) 08 Jun '23

08 Jun '23

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75726?usp=email ) Change subject: soc/mediatek/mt8195: Fix typo for SPIM2_MI ...................................................................... soc/mediatek/mt8195: Fix typo for SPIM2_MI Fix a typo in an enum type name, "PIM2_MI" -> "SPIM2_MI". TEST=emerge-cherry coreboot Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Change-Id: Ib43a044dc69a93ad1dcaa5e65c66a82046a40777 --- M src/soc/mediatek/mt8195/include/soc/gpio.h M src/soc/mediatek/mt8195/spi.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/75726/1 diff --git a/src/soc/mediatek/mt8195/include/soc/gpio.h b/src/soc/mediatek/mt8195/include/soc/gpio.h index 08fb64b..60f3af1 100644 --- a/src/soc/mediatek/mt8195/include/soc/gpio.h +++ b/src/soc/mediatek/mt8195/include/soc/gpio.h @@ -467,7 +467,7 @@ SPIM2_MO, SPINOR_IO0, SNFI_MOSI, DMIC4_DAT, RES5, RES6, DBG_MON_A12), PIN(143, SPIM2_MI, 0, 19, 0x21, 0xb0, - PIM2_MI, SPINOR_IO1, SNFI_MISO, DMIC4_CLK, + SPIM2_MI, SPINOR_IO1, SNFI_MISO, DMIC4_CLK, RES5, RES6, DBG_MON_A13), }; diff --git a/src/soc/mediatek/mt8195/spi.c b/src/soc/mediatek/mt8195/spi.c index 2772612..98b0d54 100644 --- a/src/soc/mediatek/mt8195/spi.c +++ b/src/soc/mediatek/mt8195/spi.c @@ -56,7 +56,7 @@ PAD_FUNC(SPIM1_CLK, SPIM1_CLK), }, { - PAD_FUNC(SPIM2_MI, PIM2_MI), + PAD_FUNC(SPIM2_MI, SPIM2_MI), PAD_FUNC_GPIO(SPIM2_CSB), PAD_FUNC(SPIM2_MO, SPIM2_MO), PAD_FUNC(SPIM2_CLK, SPIM2_CLK), -- To view, visit https://review.coreboot.org/c/coreboot/+/75726?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib43a044dc69a93ad1dcaa5e65c66a82046a40777 Gerrit-Change-Number: 75726 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/rex/var/screebo: Enable touchscreen
by Subrata Banik (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Kapil Porwal, Rui Zhou, Tarun Tuli, zhongtian wu. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75692?usp=email ) Change subject: mb/google/rex/var/screebo: Enable touchscreen ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Sorry, I made a mistake, it is the same screen, but the touch ic is different. As I could see the PINs are the same between two device touch device ACPI entry, I would like to make sure that only one ACPI device is getting probe eventually. hence, asked to have a FW_CONFIG. I assume that we won't be using both touch IC on a same device and if this understanding is correct then why don't we use FW_CONFIG to emulate the same HW configuration? -- To view, visit https://review.coreboot.org/c/coreboot/+/75692?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57d55c5f2621d6fafd53b19d12ecad20271cdbb1 Gerrit-Change-Number: 75692 Gerrit-PatchSet: 1 Gerrit-Owner: zhongtian wu <wuzhongtian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: zhongtian wu <wuzhongtian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 09:27:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG
by Subrata Banik (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Bernardo Perez Priego, Jamie Ryu, Jay Patel, Kapil Porwal, Li1 Feng, Tarun Tuli, Wonkyu Kim. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75525?usp=email ) Change subject: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG ...................................................................... Patch Set 8: (5 comments) Patchset: PS8: I would request the reviewer to review the code wisely rather casting the CR+2 as is. File src/mainboard/google/rex/variants/rex0/fw_config.c: https://review.coreboot.org/c/coreboot/+/75525/comment/aae612fb_02a08586 : PS8, Line 104: 1 what does `1` refer to here? https://review.coreboot.org/c/coreboot/+/75525/comment/01729542_b649b0b7 : PS8, Line 104: { why brace for single line statement ? https://review.coreboot.org/c/coreboot/+/75525/comment/29cf5951_227ebacd : PS8, Line 107: 2 what does `2` refer to here? https://review.coreboot.org/c/coreboot/+/75525/comment/7b9d5704_65fc8f03 : PS8, Line 111: printk(BIOS_ERR, "Unknown Board Version for ISH.\n"); What happens when there is board version is unknown? die ? -- To view, visit https://review.coreboot.org/c/coreboot/+/75525?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749 Gerrit-Change-Number: 75525 Gerrit-PatchSet: 8 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Jay Patel <jay2.patel(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 09:24:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG
by Subrata Banik (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Bernardo Perez Priego, Jamie Ryu, Jay Patel, Kapil Porwal, Li1 Feng, Tarun Tuli, Wonkyu Kim. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75525?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG ...................................................................... Patch Set 8: Code-Review-1 (2 comments) Patchset: PS8: i don't kw what is the board version that being looked at here File src/mainboard/google/rex/variants/rex0/fw_config.c: https://review.coreboot.org/c/coreboot/+/75525/comment/c9eb05ca_ef000d07 : PS8, Line 98: if (google_chromeec_cbi_get_board_version(&board_version)) { : printk(BIOS_ERR, : "Unable to get Board Version for ISH.\n"); : return; : } what is this board version ? -- To view, visit https://review.coreboot.org/c/coreboot/+/75525?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749 Gerrit-Change-Number: 75525 Gerrit-PatchSet: 8 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Jay Patel <jay2.patel(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 09:21:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/block/ivrs: Add NULL check for IVRS
by Naresh Solanki (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Naresh Solanki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75506?usp=email ) Change subject: soc/amd/block/ivrs: Add NULL check for IVRS ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/acpi/ivrs.c: https://review.coreboot.org/c/coreboot/+/75506/comment/5818c21e_4ab4d007 : PS1, Line 338: printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); > i'd say "ivrs is NULL". […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeb0ea3bcaa3512a93500588ad4f11046edee61f Gerrit-Change-Number: 75506 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 08 Jun 2023 09:06:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/bytedance: Add 2 SPR sockets server board bd_egs
by TangYiwei (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Jonathan Zhang, Lean Sheng Tan, Nill Ge, Patrick Rudolph, Paul Menzel, niehaitao(a)bytedance.com. TangYiwei has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75722?usp=email ) Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs ...................................................................... Patch Set 3: (25 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75722/comment/b8f0f88e_0adfa690 : PS1, Line 22: Signed-off-by: Yiwei Tang <tangyiwei.2022(a)bytedance.com> > email address 'Haitao Nie<niehaitao(a)bytedance.com>' might be better as 'Haitao Nie <niehaitao(a)bytedance.com>' Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/c336b717_ad20328c : PS1, Line 23: Reviewed-by: Haitao Nie<niehaitao(a)bytedance.com> > email address 'Shijian Ge<geshijian(a)bytedance.com>' might be better as 'Shijian Ge <geshijian(a)bytedance.com>' Please fix. File src/mainboard/bytedance/bd_egs/include/sprsp_bd_iio.h: https://review.coreboot.org/c/coreboot/+/75722/comment/03dcd6d3_eac62cd9 : PS1, Line 9: #define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp) \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/eb87a01b_9598ce41 : PS1, Line 11: .SLOTEIP = 0, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/b530bdf5_51003c3f : PS1, Line 12: .SLOTHPCAP = 0, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/cfa8b0bd_aefdeb6a : PS1, Line 13: .SLOTHPSUP = 0, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/50ec9880_014928d6 : PS1, Line 14: .SLOTPIP = 0, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/c23bd81c_03a6a31e : PS1, Line 15: .SLOTAIP = 0, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/6a6801b3_c0f74b92 : PS1, Line 16: .SLOTMRLSP = 0, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/4b593a30_bd8cd91a : PS1, Line 17: .SLOTPCP = 0, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/cb58036b_7d79bc6a : PS1, Line 18: .SLOTABP = 0, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/90a7ea5a_c8ca4d0c : PS1, Line 19: .SLOTIMP = slotimp, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/1bcb2aa5_ddca8c66 : PS1, Line 20: .SLOTSPLS = 0, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/6ae6e201_14039496 : PS1, Line 21: .SLOTSPLV = 0, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/f9ff4c48_db9ab1fa : PS1, Line 22: .SLOTPSP = slotpsp, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/d750dc64_b4770d38 : PS1, Line 23: .VppEnabled = 0, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/b927cece_23de7ae9 : PS1, Line 24: .VppPort = 0, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/88278435_519e0c91 : PS1, Line 25: .VppAddress = 0, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/8b1f3c0a_13591c31 : PS1, Line 26: .MuxAddress = 0, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/ca287b51_97084e1a : PS1, Line 27: .ChannelID = 0, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/dab36fe6_49f9319f : PS1, Line 28: .PciePortEnable = 1, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/6447a87d_ab15740f : PS1, Line 29: .PEXPHIDE = pexphide, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/90cc1003_d57dccd5 : PS1, Line 30: .HidePEXPMenu = 0, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/7fcff4a7_f9049582 : PS1, Line 31: .PciePortOwnership = 0, \ > please, no space before tabs Please fix. https://review.coreboot.org/c/coreboot/+/75722/comment/cc6acb6c_1d95d347 : PS1, Line 32: .RetimerConnectCount = 0, \ > please, no space before tabs Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/75722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d Gerrit-Change-Number: 75722 Gerrit-PatchSet: 3 Gerrit-Owner: TangYiwei Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: niehaitao(a)bytedance.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: niehaitao(a)bytedance.com Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 08:58:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/bytedance: Add 2 SPR sockets server board bd_egs
by TangYiwei (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Jonathan Zhang, Lean Sheng Tan, Nill Ge, Patrick Rudolph, Paul Menzel. Hello Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nill Ge, Patrick Rudolph, Paul Menzel, niehaitao(a)bytedance.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75722?usp=email to look at the new patch set (#2). Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs ...................................................................... mb/bytedance: Add 2 SPR sockets server board bd_egs Bytedance bd_egs is a dual socket MB with Intel Sapphire Rapids Scalable Processor chipset. Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d Co-authored-by: Jeff Li <lijinfeng01(a)ieisystem.com> Co-authored-by: Yuuka_Kazami <caolong01(a)inspur.com> Co-authored-by: wanghao11 <wanghao11(a)inspur.com> Co-authored-by: lanchenyu <lanchenyu(a)inspur.com> Co-authored-by: laykong <lay.kong(a)intel.com> Co-authored-by: kehong-intel <kehong.chen(a)intel.com> Co-authored-by: ziang <ziang.wang(a)intel.com> Co-authored-by: weidong <weidong.wd(a)bytedance.com> Co-authored-by: lichenchen.carl <lichenchen.carl(a)bytedance.com> Signed-off-by: Yiwei Tang <tangyiwei.2022(a)bytedance.com> Reviewed-by: Haitao Nie <niehaitao(a)bytedance.com> Reviewed-by: Shijian Ge <geshijian(a)bytedance.com> --- A src/mainboard/bytedance/Kconfig A src/mainboard/bytedance/Kconfig.name A src/mainboard/bytedance/bd_egs/Kconfig A src/mainboard/bytedance/bd_egs/Kconfig.name A src/mainboard/bytedance/bd_egs/Makefile.inc A src/mainboard/bytedance/bd_egs/acpi/platform.asl A src/mainboard/bytedance/bd_egs/board.fmd A src/mainboard/bytedance/bd_egs/board_info.txt A src/mainboard/bytedance/bd_egs/bootblock.c A src/mainboard/bytedance/bd_egs/devicetree.cb A src/mainboard/bytedance/bd_egs/dsdt.asl A src/mainboard/bytedance/bd_egs/gpio.c A src/mainboard/bytedance/bd_egs/gpio.h A src/mainboard/bytedance/bd_egs/include/sprsp_bd_iio.h A src/mainboard/bytedance/bd_egs/ramstage.c A src/mainboard/bytedance/bd_egs/romstage.c 16 files changed, 782 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/75722/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d Gerrit-Change-Number: 75722 Gerrit-PatchSet: 2 Gerrit-Owner: TangYiwei Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: niehaitao(a)bytedance.com Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2023