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[M] Change in coreboot[master]: UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT
by Arthur Heymans (Code Review) 08 Jun '23

08 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75729?usp=email ) Change subject: UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT ...................................................................... UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT From the Linux documentation (Documentation/PCI/acpi-info.rst): [6] PCI Firmware 3.2, sec 4.1.2: If the operating system does not natively comprehend reserving the MMCFG region, the MMCFG region must be reserved by firmware. The address range reported in the MCFG table or by _CBA method (see Section 4.1.3) must be reserved by declaring a motherboard resource. For most systems, the motherboard resource would appear at the root of the ACPI namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and the resources in this case should not be claimed in the root PCI bus’s _CRS. The resources can optionally be returned in Int15 E820 or EFIGetMemoryMap as reserved memory but must always be reported through ACPI as a motherboard resource. So in order for the OS to use ECAM MMCONF over legacy PCI IO configuration, a PNP0C02 HId device needs to reserve this region. Instead of having this code in each DSDT, add this via SSDT on all platforms with CONFIG_ECAM_MMCONF_SUPPORT. As no AMD platforms has this defined in DSDT this fixes Linux using legacy PCI IO configuration over MMCONF. For an unknown reason Linux only complained about this when it was booted with tianocore. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4 --- M src/acpi/acpi.c M src/northbridge/intel/gm45/acpi/gm45.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/i945/acpi/i945.asl M src/northbridge/intel/ironlake/acpi/ironlake.asl M src/northbridge/intel/pineview/acpi/pineview.asl M src/northbridge/intel/sandybridge/acpi/sandybridge.asl M src/northbridge/intel/x4x/acpi/x4x.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/baytrail/acpi/southcluster.asl M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/denverton_ns/acpi/northcluster.asl 12 files changed, 38 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/75729/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 4fdbd6f..a6a6212 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -570,6 +570,39 @@ acpigen_pop_len(); } +static void generate_pnp0c02_ecam(void) +{ + /* + * Device (PERC) // PCI ECAM Resource Consumption + * { + * Name (_HID, EisaId("PNP0C02")) + * Name (_UID, 1) + * Method (_CRS, 0, Serialized) + * { + * Memory32Fixed (ReadWrite, + * CONFIG_ECAM_MMCONF_BASE_ADDRESS, + * CONFIG_ECAM_MMCONF_LENGTH) + * } + */ + struct device *dev = dev_find_path(NULL, DEVICE_PATH_DOMAIN); + assert(dev != NULL); + const char *scope = acpi_device_path(dev); + acpigen_write_scope(scope); + acpigen_write_device("PERC"); + acpigen_write_name("_HID"); + acpigen_emit_eisaid("PNP0C02"); + acpigen_write_name_integer("_UID", 1); + + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpigen_write_mem32fixed(1, CONFIG_ECAM_MMCONF_BASE_ADDRESS, + CONFIG_ECAM_MMCONF_LENGTH); + acpigen_write_resourcetemplate_footer(); + acpigen_pop_len(); // device + acpigen_pop_len(); // scope + +} + static void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) { unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t); @@ -595,9 +628,13 @@ for (dev = all_devices; dev; dev = dev->next) if (dev->enabled && dev->ops && dev->ops->acpi_fill_ssdt) dev->ops->acpi_fill_ssdt(dev); - current = (unsigned long)acpigen_get_current(); } + if (CONFIG(ECAM_MMCONF_SUPPORT)) + generate_pnp0c02_ecam(); + + current = (unsigned long)acpigen_get_current(); + /* (Re)calculate length and checksum. */ ssdt->length = current - (unsigned long)ssdt; ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index c4636be..4e86092 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -16,7 +16,6 @@ Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 513e960..3ecc5b3 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -178,7 +178,6 @@ Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE) Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE) Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE) - Memory32Fixed (ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index f935b71..733b782 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -40,7 +40,6 @@ Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl index b4bd8e9..f64ded4 100644 --- a/src/northbridge/intel/ironlake/acpi/ironlake.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -14,7 +14,6 @@ Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00008000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 4901c21..ab7bbcd 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -15,7 +15,6 @@ Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */ Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */ Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */ diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index cf1d61c..f269bf4 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -15,7 +15,6 @@ Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB) Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB) Memory32Fixed(ReadWrite, 0, 0x00001000, EGPB) - Memory32Fixed(ReadWrite, 0, 0x04000000, PCIX) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // TPM TIS Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH @@ -37,12 +36,6 @@ CreateDwordField (PDRS, ^EGPB._BAS, EBR0) EBR0 = \_SB.PCI0.MCHC.EPBR << 12 - CreateDwordField (PDRS, ^PCIX._BAS, XBR0) - XBR0 = \_SB.PCI0.MCHC.PXBR << 26 - - CreateDwordField (PDRS, ^PCIX._LEN, XSZ0) - XSZ0 = 0x10000000 >> \_SB.PCI0.MCHC.PXSZ - Return(PDRS) } } diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 462cdf9..5425867c 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -13,7 +13,6 @@ Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 1b47509..a304331 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -116,11 +116,6 @@ { Name (BUF0, ResourceTemplate () { - /* PCI Express BAR */ - Memory32Fixed (ReadWrite, - CONFIG_ECAM_MMCONF_BASE_ADDRESS, - CONFIG_ECAM_MMCONF_LENGTH, PCIX) - /* Local APIC range (0xfee0_0000 to 0xfeef_ffff) */ Memory32Fixed (ReadOnly, 0x0fee00000, 0x00010000, LIOH) }) diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index dacdd29..131825e 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -189,7 +189,6 @@ Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) - Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index 3dcc6c1..1e52df1 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -188,7 +188,6 @@ Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) - Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl index e415dc4..ce687dd 100644 --- a/src/soc/intel/denverton_ns/acpi/northcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl @@ -121,8 +121,6 @@ Name (_UID, 1) Name (PDRS, ResourceTemplate() { - // PCIEXBAR memory range - Memory32Fixed(ReadOnly, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) // TSEG Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, TSMB) }) -- To view, visit https://review.coreboot.org/c/coreboot/+/75729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4 Gerrit-Change-Number: 75729 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: acpi: Add a debug option to print out tables in ACPICA compatible hex
by Nico Huber (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Arthur Heymans, Benjamin Doron, Kyösti Mälkki, Lance Zhao, Lean Sheng Tan, Paul Menzel, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75677?usp=email ) Change subject: acpi: Add a debug option to print out tables in ACPICA compatible hex ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc Gerrit-Change-Number: 75677 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 13:27:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[NoOp] Change in blobs[master]: mb/google/skyrim/var/markarth: Add custom ABL
by Jon Murphy (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Karthik Ramasubramanian, Martin Roth, Paul Menzel. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/75693?usp=email ) Change subject: mb/google/skyrim/var/markarth: Add custom ABL ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/blobs/+/75693/comment/69b6245d_866863ff : PS2, Line 12: Add custom ABL to resolve boot issues during reset. > I’d add a blank line between paragraphs. (Feel free to ignore. […] Acknowledged -- To view, visit https://review.coreboot.org/c/blobs/+/75693?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I3e48a16e0a46b2948260fd427b76a2ed88303996 Gerrit-Change-Number: 75693 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 13:22:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[NoOp] Change in blobs[master]: mb/google/skyrim/var/markarth: Add custom ABL
by Jon Murphy (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Jon Murphy, Karthik Ramasubramanian, Martin Roth. Hello Karthik Ramasubramanian, Martin Roth, Tim Van Patten, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/blobs/+/75693?usp=email to look at the new patch set (#3). Change subject: mb/google/skyrim/var/markarth: Add custom ABL ...................................................................... mb/google/skyrim/var/markarth: Add custom ABL Markarth hangs at 0xea00e0w during FAFT warm reset process. This appears to be due to timing characteristics of the DDR parts deviating from the spec. Add custom ABL to resolve boot issues during reset. BUG=b:281614369 TEST=Build Skyrim and Markarth BIOS image. Ensure that the right ABL binary is getting picked up. Change-Id: I3e48a16e0a46b2948260fd427b76a2ed88303996 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- A mainboard/google/skyrim/variants/markarth/TypeId0x30_AgesaBootloaderU_MDN_LPDDR5.sbin 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/93/75693/3 -- To view, visit https://review.coreboot.org/c/blobs/+/75693?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I3e48a16e0a46b2948260fd427b76a2ed88303996 Gerrit-Change-Number: 75693 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: acpi: Add a debug option to print out tables in ACPICA compatible hex
by Arthur Heymans (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Benjamin Doron, Kyösti Mälkki, Lance Zhao, Lean Sheng Tan, Nico Huber, Paul Menzel, Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75677?usp=email ) Change subject: acpi: Add a debug option to print out tables in ACPICA compatible hex ...................................................................... Patch Set 6: (1 comment) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/75677/comment/66d15012_b48f06ff : PS5, Line 1874: .4%s > .4 behind % Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc Gerrit-Change-Number: 75677 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 13:20:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: acpi: Add a debug option to print out tables in ACPICA compatible hex
by Arthur Heymans (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Arthur Heymans, Benjamin Doron, Kyösti Mälkki, Lance Zhao, Lean Sheng Tan, Nico Huber, Paul Menzel, Tim Wawrzynczak. Hello Benjamin Doron, Kyösti Mälkki, Lance Zhao, Lean Sheng Tan, Nico Huber, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75677?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+1 by Kyösti Mälkki, Code-Review+2 by Lean Sheng Tan, Code-Review+2 by Tim Wawrzynczak, Code-Review-1 by Arthur Heymans, Verified+1 by build bot (Jenkins) Change subject: acpi: Add a debug option to print out tables in ACPICA compatible hex ...................................................................... acpi: Add a debug option to print out tables in ACPICA compatible hex Sometimes systems don't boot to the OS due to wrong ACPI tables. Printing the tables in an ACPICA compatible format makes analysis of ACPI tables easier. The ACPICA format (acpidump, acpixtract) is the following: " FACS @ 0x0000000000000000 0000: 46 41 43 53 40 00 00 00 E8 24 00 00 00 00 00 00 FACS@....$...... 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ " To achieve analyze ACPI tables capture the coreboot log between "Printing ACPI in ACPICA compatible table" and "Done printing ACPI in ACPICA compatible table". Remove the prefix "[SPEW ] " and then call 'acpixtract -a dump' to extract all the tables. Then use 'iasl -d' on the .dat files to decompile the tables. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc --- M src/Kconfig M src/acpi/acpi.c 2 files changed, 93 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/75677/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/75677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc Gerrit-Change-Number: 75677 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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[NoOp] Change in blobs[master]: mb/google/skyrim/var/markarth: Add custom ABL
by Paul Menzel (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Jon Murphy, Karthik Ramasubramanian, Martin Roth. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/75693?usp=email ) Change subject: mb/google/skyrim/var/markarth: Add custom ABL ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/blobs/+/75693/comment/3cba49b4_584b7652 : PS2, Line 12: Add custom ABL to resolve boot issues during reset. I’d add a blank line between paragraphs. (Feel free to ignore.) -- To view, visit https://review.coreboot.org/c/blobs/+/75693?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I3e48a16e0a46b2948260fd427b76a2ed88303996 Gerrit-Change-Number: 75693 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 13:19:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[NoOp] Change in blobs[master]: mb/google/skyrim/var/markarth: Add custom ABL
by Jon Murphy (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Karthik Ramasubramanian, Martin Roth, Paul Menzel. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/75693?usp=email ) Change subject: mb/google/skyrim/var/markarth: Add custom ABL ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/blobs/+/75693/comment/02a16330_5ce9d04a : PS1, Line 9: boot issues during reset > It’d be great if you elaborated. Done https://review.coreboot.org/c/blobs/+/75693/comment/368df98c_61c57e11 : PS1, Line 10: > If you could document how that issue was fixed in ABL, that’d be great too. I don't have much insight into the fix. This was pulled into the chromium internal repo and I'm now trying to align upstream. Patchset: PS1: > This change itself looks good. […] ACK -- To view, visit https://review.coreboot.org/c/blobs/+/75693?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I3e48a16e0a46b2948260fd427b76a2ed88303996 Gerrit-Change-Number: 75693 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 13:10:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[NoOp] Change in blobs[master]: mb/google/skyrim/var/markarth: Add custom ABL
by Jon Murphy (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Jon Murphy, Martin Roth. Hello Karthik Ramasubramanian, Martin Roth, Tim Van Patten, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/blobs/+/75693?usp=email to look at the new patch set (#2). Change subject: mb/google/skyrim/var/markarth: Add custom ABL ...................................................................... mb/google/skyrim/var/markarth: Add custom ABL Markarth hangs at 0xea00e0w during FAFT warm reset process. This appears to be due to timing characteristics of the DDR parts deviating from the spec. Add custom ABL to resolve boot issues during reset. BUG=b:281614369 TEST=Build Skyrim and Markarth BIOS image. Ensure that the right ABL binary is getting picked up. Change-Id: I3e48a16e0a46b2948260fd427b76a2ed88303996 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- A mainboard/google/skyrim/variants/markarth/TypeId0x30_AgesaBootloaderU_MDN_LPDDR5.sbin 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/93/75693/2 -- To view, visit https://review.coreboot.org/c/blobs/+/75693?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I3e48a16e0a46b2948260fd427b76a2ed88303996 Gerrit-Change-Number: 75693 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: acpi: Add a debug option to print out tables in ACPICA compatible hex
by Arthur Heymans (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Benjamin Doron, Lance Zhao, Nico Huber, Paul Menzel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75677?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: acpi: Add a debug option to print out tables in ACPICA compatible hex ...................................................................... Patch Set 5: Code-Review-1 (1 comment) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/75677/comment/e772d339_79ba6893 : PS5, Line 1874: .4%s .4 behind % -- To view, visit https://review.coreboot.org/c/coreboot/+/75677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc Gerrit-Change-Number: 75677 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 08 Jun 2023 13:10:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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