coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: soc/amd/picasso/acpi/northbridge: drop _STA method from PCI0 scope
by Felix Held (Code Review) 08 Jun '23

08 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74993?usp=email ) Change subject: soc/amd/picasso/acpi/northbridge: drop _STA method from PCI0 scope ...................................................................... soc/amd/picasso/acpi/northbridge: drop _STA method from PCI0 scope The PCI root complex itself isn't on an enumerable bus, so without providing an _STA method, the device will still be assumed to be present and visible, so this won't change behavior. This also brings Picasso more in line with Cezanne and newer SoCs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Nico Huber <nico.h(a)gmx.de> Change-Id: Ied48b48113f6e871e90d17cbd216be003f05b5ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/74993 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/picasso/acpi/northbridge.asl 1 file changed, 0 insertions(+), 5 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl index 5cbe950..bec9b46 100644 --- a/src/soc/amd/picasso/acpi/northbridge.asl +++ b/src/soc/amd/picasso/acpi/northbridge.asl @@ -2,11 +2,6 @@ /* Describe the Northbridge devices */ -Method(_STA, 0, NotSerialized) -{ - Return(0x0f) /* Status is visible */ -} - /* PCI Routing Table */ Name(PR0, Package(){ /* Bus 0, Dev 0x00 - F2: IOMMU */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74993?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied48b48113f6e871e90d17cbd216be003f05b5ef Gerrit-Change-Number: 74993 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/amd/phoenix: Hook up xhci ops in chipset.cb
by Felix Held (Code Review) 08 Jun '23

08 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75659?usp=email ) Change subject: soc/amd/phoenix: Hook up xhci ops in chipset.cb ...................................................................... soc/amd/phoenix: Hook up xhci ops in chipset.cb Hook up xhci ops for Phoenix xHCI device. Benefit is we don't have to bother by adding xhci DID. BUG=b:285981912 TEST=check coreboot log shows below. [INFO ] \_SB.PCI0.GP41.XHC0.RHUB.SS01: USB3 Type-A Port A0 (MLB) Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: Ib59874948725966b04b54def3f6de463afeda709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75659 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/drivers/usb/pci_xhci/pci_xhci.c M src/soc/amd/phoenix/chipset.cb 2 files changed, 6 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/drivers/usb/pci_xhci/pci_xhci.c b/src/drivers/usb/pci_xhci/pci_xhci.c index 63a98c7..ca51278 100644 --- a/src/drivers/usb/pci_xhci/pci_xhci.c +++ b/src/drivers/usb/pci_xhci/pci_xhci.c @@ -12,7 +12,7 @@ #define PCI_XHCI_CLASSCODE 0x0c0330 /* USB3.0 xHCI controller */ static unsigned int controller_count; -static const struct device_operations xhci_pci_ops; +const struct device_operations xhci_pci_ops; struct port_counts { unsigned int high_speed; @@ -240,7 +240,7 @@ dev->name = name; } -static const struct device_operations xhci_pci_ops = { +const struct device_operations xhci_pci_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index 6525936..12bb2fe 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -38,6 +38,7 @@ device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor device pci 0.3 alias xhci_0 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_0_root_hub off @@ -66,6 +67,7 @@ end end device pci 0.4 alias xhci_1 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_1_root_hub off @@ -92,6 +94,7 @@ ops amd_internal_pcie_gpp_ops device pci 0.0 on end # dummy, do not disable device pci 0.3 alias usb4_xhci_0 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias usb4_xhci_0_root_hub off @@ -105,6 +108,7 @@ end end device pci 0.4 alias usb4_xhci_1 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias usb4_xhci_1_root_hub off -- To view, visit https://review.coreboot.org/c/coreboot/+/75659?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib59874948725966b04b54def3f6de463afeda709 Gerrit-Change-Number: 75659 Gerrit-PatchSet: 7 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/*/root_complex: reserve IOMMU MMIO area
by Felix Held (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Arthur Heymans, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75611?usp=email ) Change subject: soc/amd/*/root_complex: reserve IOMMU MMIO area ...................................................................... Patch Set 4: (2 comments) Patchset: PS2: > need to do this for the other socs too Done File src/soc/amd/common/block/include/amdblocks/iomap.h: https://review.coreboot.org/c/coreboot/+/75611/comment/df15bad6_d63e0517 : PS4, Line 15: 0xfd00000000 > That's typically where the full SPI flash is mapped too right (ROM3 register)? […] hmm, i'd need to have a closer look at this next week. somewhere at the beginning of the data fabric chapter the ppr says that most of this area is reserved for the iommu. there are 3 regions that cover more or less the full 4GB region, but might be that something else is in between those -- To view, visit https://review.coreboot.org/c/coreboot/+/75611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a8150873cb019ca1d903ed269e18d6f9fabb871 Gerrit-Change-Number: 75611 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 15:50:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/mediatek/common: Disable DRAM scramble by default
by Hung-Te Lin (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Paul Menzel, Yidi Lin, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75562?usp=email ) Change subject: soc/mediatek/common: Disable DRAM scramble by default ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75562/comment/e99c694e_e4e07a95 : PS3, Line 11: and > Sorry, I am having trouble to understand the *and*. […] No, we currently don't plan to enable this feature in production. Probably change the 'and' to 'to'? -- To view, visit https://review.coreboot.org/c/coreboot/+/75562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I109634d811a928e3e6f7f56e706a5b61a52a21ab Gerrit-Change-Number: 75562 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 15:50:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT
by Paul Menzel (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Jeff Daly, Lance Zhao, Matt DeVillier, Sean Rhodes, Tim Wawrzynczak, Vanessa Eusebio. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75729?usp=email ) Change subject: UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75729/comment/3e4265a0_283fff5f : PS2, Line 23: HId HID -- To view, visit https://review.coreboot.org/c/coreboot/+/75729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4 Gerrit-Change-Number: 75729 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 08 Jun 2023 15:42:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/dedede/var/dibbi: Update power limits
by ChiaLing (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Reka Norman, Ryan Lin, Zhuohao Lee. Hello Reka Norman, Ryan Lin, Zhuohao Lee, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75681?usp=email to look at the new patch set (#5). Change subject: mb/google/dedede/var/dibbi: Update power limits ...................................................................... mb/google/dedede/var/dibbi: Update power limits Add ramstage.c in Makefile.inc and update Dibbi power limit in ramstage BUG=b:281479111 TEST=emerge-dedede coreboot and check psys and PLx value on dibbi Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com> Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6 --- M src/mainboard/google/dedede/variants/dibbi/Makefile.inc A src/mainboard/google/dedede/variants/dibbi/ramstage.c 2 files changed, 73 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/75681/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/75681?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6 Gerrit-Change-Number: 75681 Gerrit-PatchSet: 5 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/myst: Add pen detect support
by Tim Van Patten (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Eric Lai, Jon Murphy, Martin Roth. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75696?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/myst: Add pen detect support ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/google/myst/variants/myst/overridetree.cb: https://review.coreboot.org/c/coreboot/+/75696/comment/3d1540f6_32fc2090 : PS1, Line 77: device generic 0 on end It's outside of the scope of this CL, but according to go/myst-skus we don't have a field to indicate whether a stylus is present or not, so we can't probe for it. Instead, we always enable it for all Myst boards. Should we open a bug to add that, like we did for Frostflow? - b/260473966 - https://review.coreboot.org/c/coreboot/+/70418 -- To view, visit https://review.coreboot.org/c/coreboot/+/75696?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I922d643a83c5cd8ea0ab9fe6733f7aa05d935802 Gerrit-Change-Number: 75696 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 15:35:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/dedede: Support variant specific power limits
by ChiaLing (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Paul Menzel, Reka Norman, Ryan Lin, Zhuohao Lee. ChiaLing has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75680?usp=email ) Change subject: mb/google/dedede: Support variant specific power limits ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75680/comment/97db6a3a_5c4b96c8 : PS3, Line 11: adapter. > Fits on the line above. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/75680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I583c930379233322c41027805369f81d02000ee7 Gerrit-Change-Number: 75680 Gerrit-PatchSet: 4 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 15:26:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/dedede: Support variant specific power limits
by ChiaLing (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: ChiaLing, Reka Norman, Ryan Lin, Zhuohao Lee. Hello Reka Norman, Ryan Lin, Zhuohao Lee, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75680?usp=email to look at the new patch set (#4). Change subject: mb/google/dedede: Support variant specific power limits ...................................................................... mb/google/dedede: Support variant specific power limits With newer dedede design, it's required to config corresponding psyspmax, psyspl1, psyspl2, pl1 and pl2 by different kind of adapter. BUG=b:281479111 TEST=emerge-dedede coreboot and check correct value on dibbi Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com> Change-Id: I583c930379233322c41027805369f81d02000ee7 --- M src/mainboard/google/dedede/variants/baseboard/Makefile.inc M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/dedede/variants/baseboard/ramstage.c 3 files changed, 212 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/75680/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/75680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I583c930379233322c41027805369f81d02000ee7 Gerrit-Change-Number: 75680 Gerrit-PatchSet: 4 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/google/brya/acpi: Turn NV12 enable signal off on GCOFF entry
by Tarun Tuli (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Paul Menzel. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75533?usp=email ) Change subject: mb/google/brya/acpi: Turn NV12 enable signal off on GCOFF entry ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75533/comment/5d0ff2d9_d1195b61 : PS5, Line 7: NV12 enable signal should be off on GCOFF entry > Please make it a statement about the action and not a problem description – like you do in the body. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d338fc4a96f119617aff558413a5a9ac44c27d7 Gerrit-Change-Number: 75533 Gerrit-PatchSet: 6 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 08 Jun 2023 15:22:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit June 2023