coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: arch/risc/mcall.h: Make the stack pointer global
by Arthur Heymans (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Angel Pons, Felix Singer, Philipp Hug, Ron Minnich. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74570?usp=email ) Change subject: arch/risc/mcall.h: Make the stack pointer global ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74570/comment/0ffe2744_616b7ac1 : PS4, Line 10: remediated > be remediated Done https://review.coreboot.org/c/coreboot/+/74570/comment/7a4907fc_b943c1b9 : PS4, Line 10: Change > Change... […] Done Patchset: PS4: > No idea how this is supposed to work. Has it been tested? Risc-v support is broken since ~4 years. TESTED with the fix https://review.coreboot.org/c/coreboot/+/36486/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24602372833aa9d413bf396853b223263fd873ed Gerrit-Change-Number: 74570 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 17:59:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: acpi/acpi.c: Reduce scope of functions used locally
by Arthur Heymans (Code Review) 08 Jun '23

08 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75732?usp=email ) Change subject: acpi/acpi.c: Reduce scope of functions used locally ...................................................................... acpi/acpi.c: Reduce scope of functions used locally Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ieca5d8d175923f690ebfa3108e393e029ea97c80 --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 5 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/75732/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 4fdbd6f..6ee5cf4 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -110,7 +110,7 @@ i + 1, entries_num, rsdt->header.length); } -int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, +static int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, u16 seg_nr, u8 start, u8 end) { memset(mmconfig, 0, sizeof(*mmconfig)); @@ -197,7 +197,7 @@ return current; } -int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, +static int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, u32 gsi_base) { ioapic->type = IO_APIC; /* I/O APIC structure */ @@ -244,7 +244,7 @@ #endif } -int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, +static int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, u8 bus, u8 source, u32 gsirq, u16 flags) { irqoverride->type = IRQ_SOURCE_OVERRIDE; /* Interrupt source override */ @@ -257,7 +257,7 @@ return irqoverride->length; } -int acpi_create_madt_sci_override(acpi_madt_irqoverride_t *irqoverride) +static int acpi_create_madt_sci_override(acpi_madt_irqoverride_t *irqoverride) { u8 gsi, irq, flags; @@ -331,7 +331,7 @@ return current; } -unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current) +static unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current) { current = acpi_create_madt_lapics(current); current = acpi_create_madt_lapic_nmis(current); diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 78a6005..c6558af 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1333,15 +1333,9 @@ int acpi_create_cedt_cfmws(acpi_cedt_cfmws_t *cfmws, u64 base_hpa, u64 window_size, u8 eniw, u32 hbig, u16 restriction, u16 qtg_id, const u32 *interleave_target); -int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, - u32 gsi_base); int acpi_create_madt_ioapic_from_hw(acpi_madt_ioapic_t *ioapic, u32 addr); -int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, - u8 bus, u8 source, u32 gsirq, u16 flags); -int acpi_create_madt_sci_override(acpi_madt_irqoverride_t *irqoverride); unsigned long acpi_create_madt_one_lapic(unsigned long current, u32 cpu, u32 apic); -unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current); unsigned long acpi_create_madt_lapic_nmis(unsigned long current); @@ -1355,8 +1349,6 @@ */ int acpi_create_srat_gia_pci(acpi_srat_gia_t *gia, u32 proximity_domain, u16 seg, u8 bus, u8 dev, u8 func, u32 flags); -int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, - u16 seg_nr, u8 start, u8 end); unsigned long acpi_create_srat_lapics(unsigned long current); void acpi_create_srat(acpi_srat_t *srat, unsigned long (*acpi_fill_srat)(unsigned long current)); -- To view, visit https://review.coreboot.org/c/coreboot/+/75732?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieca5d8d175923f690ebfa3108e393e029ea97c80 Gerrit-Change-Number: 75732 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG
by Subrata Banik (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Bernardo Perez Priego, Jamie Ryu, Jay Patel, Kapil Porwal, Li1 Feng, Tarun Tuli, Wonkyu Kim. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75525?usp=email ) Change subject: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG ...................................................................... Patch Set 8: (2 comments) File src/mainboard/google/rex/variants/rex0/fw_config.c: https://review.coreboot.org/c/coreboot/+/75525/comment/7ca2e8e3_3751fab2 : PS8, Line 104: 1 > I assumed that this CBI should be the mechanism to determine if Proto1 or Proto2. > If this should not be the way, could you please suggest any other method to differentiate them? I don't understand the Proto 1 vs Proto 2 dependency. Are you expecting to see different PIN between Proto 1 vs Proto 2? If yes, then the latest HW is what we should be supporting (which is Proto 1 until we have Proto 2) https://review.coreboot.org/c/coreboot/+/75525/comment/b9657c8b_6e3f1728 : PS8, Line 111: printk(BIOS_ERR, "Unknown Board Version for ISH.\n"); > I assumed that it would not configure any GPIO pin if board was not determined. what is the downside, will system be able to enter S0ix ? will we observe any abnormalities ? if yes, then better to die -- To view, visit https://review.coreboot.org/c/coreboot/+/75525?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749 Gerrit-Change-Number: 75525 Gerrit-PatchSet: 8 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Jay Patel <jay2.patel(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 17:51:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetree
by Jon Murphy (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Felix Held, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier, Raul Rangel. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75713?usp=email ) Change subject: soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetree ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75713?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c455002c6d2aac576fe24eee0c31744b4507bb0 Gerrit-Change-Number: 75713 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 08 Jun 2023 17:45:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAM
by Matt DeVillier (Code Review) 08 Jun '23

08 Jun '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75698?usp=email ) Change subject: mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAM ...................................................................... mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAM One specific Hynix LPDDR5x DRAM part requires an ABL workaround to eliminate DRAM-related failures during a FAFT test, but due to the use of generic/common SPDs, there is no way for the ABL to determine the DRAM part # itself. Until the issue can be root-caused, we will have coreboot check the DRAM part #, and set/clear a CMOS bit as appropriate, which the ABL will check in order to apply (or not apply) the workaround. The ABL uses already uses byte 0xD of the extended CMOS ports 72/73 for memory context related toggles, so we will use a spare bit there. BUG=b:270499009, b:281614369, b:286338775 BRANCH=skyrim TEST=run FAFT bios tests on frostflow, markarth, and whiterun without any failures. Change-Id: Ibb6e145f6cdba7270e0a322ef414bf1cb09c5eaa Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/skyrim/bootblock.c 1 file changed, 59 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/75698/1 diff --git a/src/mainboard/google/skyrim/bootblock.c b/src/mainboard/google/skyrim/bootblock.c index 4128090..16c9201 100644 --- a/src/mainboard/google/skyrim/bootblock.c +++ b/src/mainboard/google/skyrim/bootblock.c @@ -1,9 +1,66 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/espi.h> +#include <amdblocks/reset.h> #include <bootblock_common.h> #include <baseboard/variants.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <pc80/mc146818rtc.h> #include <soc/espi.h> +#include <string.h> + +#define CMOS_EXTENDED_ADDR(x) (128 + (x)) +#define CMOS_MEM_RESTORE_OFFSET 0x0D +#define CMOS_BITMAP_SKIP_RESET_TOGGLE 0x10 +#define HYNIX_PART_NAME "H9JCNNNCP3MLYR-N6E" +#define HYNIX_PART_LEN 18 + +/* Ensure SKIP_RESET_TOGGLE CMOS bit set for problematic Hynix part, cleared otherwise */ +static void hynix_dram_cmos_check(void) +{ + char cbi_part_number[DIMM_INFO_PART_NUMBER_SIZE]; + bool skip_reset_toggle, cmos_bit_set; + unsigned char byte_value; + + byte_value = cmos_read(CMOS_EXTENDED_ADDR(CMOS_MEM_RESTORE_OFFSET)); + cmos_bit_set = (byte_value & CMOS_BITMAP_SKIP_RESET_TOGGLE) != 0; + + printk(BIOS_SPEW, "Checking DRAM part #\n"); + + /* Get RAM module part # from CBI */ + if (google_chromeec_cbi_get_dram_part_num( + cbi_part_number, sizeof(cbi_part_number)) != 0) { + printk(BIOS_ERR, "Unable to read DRAM part # from CBI\n"); + return; + } + /* Ensure DRAM part # null terminated */ + cbi_part_number[DIMM_INFO_PART_NUMBER_SIZE - 1] = 0; + printk(BIOS_SPEW, "DRAM part # is %s\n", cbi_part_number); + + skip_reset_toggle = strncmp(cbi_part_number, HYNIX_PART_NAME, HYNIX_PART_LEN) == 0; + + /* If problematic Hynix module, ensure bit set */ + if (skip_reset_toggle) { + printk(BIOS_SPEW, "SKIP_RESET_TOGGLE needed, checking CMOS bit is set\n"); + /* if flag unset, set and reboot so memory re-trained */ + if (!cmos_bit_set) { + printk(BIOS_SPEW, "Bit is unset; setting and rebooting\n"); + cmos_write((byte_value | CMOS_BITMAP_SKIP_RESET_TOGGLE), + CMOS_EXTENDED_ADDR(CMOS_MEM_RESTORE_OFFSET)); + warm_reset(); + } + printk(BIOS_SPEW, "Bit already set; nothing to do.\n"); + } else if (cmos_bit_set) { + /* Otherwise, ensure SKIP_RESET_TOGGLE bit cleared */ + printk(BIOS_SPEW, "CMOS SKIP_RESET_TOGGLE bit is set; clearing and rebooting\n"); + cmos_write((byte_value & ~CMOS_BITMAP_SKIP_RESET_TOGGLE), + CMOS_EXTENDED_ADDR(CMOS_MEM_RESTORE_OFFSET)); + warm_reset(); + } else { + printk(BIOS_SPEW, "No change to CMOS SKIP_RESET_TOGGLE bit is needed\n"); + } +} void mb_set_up_early_espi(void) { @@ -34,6 +91,8 @@ size_t num_gpios; const struct soc_amd_gpio *gpios; + hynix_dram_cmos_check(); + variant_bootblock_gpio_table(&gpios, &num_gpios); gpio_configure_pads(gpios, num_gpios); } -- To view, visit https://review.coreboot.org/c/coreboot/+/75698?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6e145f6cdba7270e0a322ef414bf1cb09c5eaa Gerrit-Change-Number: 75698 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/myst/bootblock.c: Initialize spi flash
by Fred Reitberger (Code Review) 08 Jun '23

08 Jun '23

Fred Reitberger has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75588?usp=email ) Change subject: mb/google/myst/bootblock.c: Initialize spi flash ...................................................................... mb/google/myst/bootblock.c: Initialize spi flash Initialize the SPI Flash in bootblock to ensure that CONFIG_SPI_FLASH_EXIT_4_BYTE_ADDR_MODE will exit 4-byte addressing mode. BUG=b:285110121 TEST=boot myst and verify flash operations work correctly Change-Id: Ia88d2b46884b096b4c558bc86513159ec6d35eb5 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75588 Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/myst/bootblock.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jon Murphy: Looks good to me, approved diff --git a/src/mainboard/google/myst/bootblock.c b/src/mainboard/google/myst/bootblock.c index 4404666..29d0a5a 100644 --- a/src/mainboard/google/myst/bootblock.c +++ b/src/mainboard/google/myst/bootblock.c @@ -3,7 +3,9 @@ #include <amdblocks/espi.h> #include <bootblock_common.h> #include <baseboard/variants.h> +#include <console/console.h> #include <soc/espi.h> +#include <spi_flash.h> void mb_set_up_early_espi(void) { @@ -35,4 +37,8 @@ variant_bootblock_gpio_table(&gpios, &num_gpios); gpio_configure_pads(gpios, num_gpios); + + // TODO: b:285110121 - temp workaround is to add a dummy flash call + const struct spi_flash *spi = boot_device_spi_flash(); + printk(BIOS_DEBUG, "Initialized spi flash %p\n", spi); } -- To view, visit https://review.coreboot.org/c/coreboot/+/75588?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia88d2b46884b096b4c558bc86513159ec6d35eb5 Gerrit-Change-Number: 75588 Gerrit-PatchSet: 3 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/google/myst/bootblock.c: Initialize spi flash
by Jon Murphy (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Martin L Roth, Martin Roth. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75588?usp=email ) Change subject: mb/google/myst/bootblock.c: Initialize spi flash ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75588?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia88d2b46884b096b4c558bc86513159ec6d35eb5 Gerrit-Change-Number: 75588 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 08 Jun 2023 17:38:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/amd/mayan:Enable the DT and M.2 SSD1 PCIE slots
by Fred Reitberger (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Anand Vaikar, Felix Held, Jason Glenesk, Matt DeVillier, Paul Menzel, ritul guru. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74069?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/amd/mayan:Enable the DT and M.2 SSD1 PCIE slots ...................................................................... Patch Set 14: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74069/comment/7f4f81f7_a6b62b78 : PS6, Line 8: > Done Looks like this was lost in the latest patch set. -- To view, visit https://review.coreboot.org/c/coreboot/+/74069?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id141e5e55ef6e25722b411975a59c9764b86f624 Gerrit-Change-Number: 74069 Gerrit-PatchSet: 14 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 08 Jun 2023 17:37:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG
by Bernardo Perez Priego (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Jamie Ryu, Jay Patel, Kapil Porwal, Li1 Feng, Subrata Banik, Tarun Tuli, Wonkyu Kim. Bernardo Perez Priego has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75525?usp=email ) Change subject: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG ...................................................................... Patch Set 8: (4 comments) File src/mainboard/google/rex/variants/rex0/fw_config.c: https://review.coreboot.org/c/coreboot/+/75525/comment/ab6baf91_f869cfba : PS8, Line 104: 1 > what does `1` refer to here? I assumed that this CBI should be the mechanism to determine if Proto1 or Proto2. If this should not be the way, could you please suggest any other method to differentiate them? https://review.coreboot.org/c/coreboot/+/75525/comment/f4ba096b_0f4c9711 : PS8, Line 104: { > why brace for single line statement ? Acknowledged https://review.coreboot.org/c/coreboot/+/75525/comment/8741ab96_3355f497 : PS8, Line 107: 2 > what does `2` refer to here? Same as above comment. https://review.coreboot.org/c/coreboot/+/75525/comment/ec7013ef_90c691b8 : PS8, Line 111: printk(BIOS_ERR, "Unknown Board Version for ISH.\n"); > What happens when there is board version is unknown? […] I assumed that it would not configure any GPIO pin if board was not determined. -- To view, visit https://review.coreboot.org/c/coreboot/+/75525?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749 Gerrit-Change-Number: 75525 Gerrit-PatchSet: 8 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Jay Patel <jay2.patel(a)intel.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 17:32:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/brya/var/kano: Add Micron MT53E2G32D4NQ-046 WT:C SPD
by Nick Vaccaro (Code Review) 08 Jun '23

08 Jun '23

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75716?usp=email ) Change subject: mb/google/brya/var/kano: Add Micron MT53E2G32D4NQ-046 WT:C SPD ...................................................................... mb/google/brya/var/kano: Add Micron MT53E2G32D4NQ-046 WT:C SPD Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM. BUG=b:216393391 TEST=build pass Change-Id: I0abf1f1105f9a6f16af23b0ed3eb4faeb669eee6 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75716 Reviewed-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/kano/memory/Makefile.inc M src/mainboard/google/brya/variants/kano/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tyler Wang: Looks good to me, but someone else must approve Derek Huang: Looks good to me, approved Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kano/memory/Makefile.inc b/src/mainboard/google/brya/variants/kano/memory/Makefile.inc index c526aa0..5cea376 100644 --- a/src/mainboard/google/brya/variants/kano/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/kano/memory/Makefile.inc @@ -6,3 +6,4 @@ SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 2(0b0010) Parts = MT53E2G32D4NQ-046 WT:C diff --git a/src/mainboard/google/brya/variants/kano/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/kano/memory/dram_id.generated.txt index 6b0c25f..de8c399 100644 --- a/src/mainboard/google/brya/variants/kano/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/kano/memory/dram_id.generated.txt @@ -10,3 +10,4 @@ H54G56CYRBX247 1 (0001) K4U6E3S4AB-MGCL 0 (0000) K4UBE3D4AB-MGCL 1 (0001) +MT53E2G32D4NQ-046 WT:C 2 (0010) diff --git a/src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt index a188982..eab1b17 100644 --- a/src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt @@ -4,3 +4,4 @@ H54G56CYRBX247 K4U6E3S4AB-MGCL K4UBE3D4AB-MGCL +MT53E2G32D4NQ-046 WT:C -- To view, visit https://review.coreboot.org/c/coreboot/+/75716?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0abf1f1105f9a6f16af23b0ed3eb4faeb669eee6 Gerrit-Change-Number: 75716 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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