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Change subject: mb/google/myst: Update PCIE_RST_L drive
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/75700/comment/b5c9b82d_a4c8b918 :
PS2, Line 55: PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
NF is interned change? If so, better mention in comment.
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Patch Set 6: Code-Review+2
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Change subject: mb/google/myst: Update PCIe romstage gpios
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/75699/comment/a35bf24b_76bfd221 :
PS1, Line 203: /* SSD_AUX_RESET */
> Recommend doing the same for SD as well since that also needs to be brought out of reset before PCIe […]
Done
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Hello Eric Lai, Karthik Ramasubramanian, Martin Roth, Tim Van Patten,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75699?usp=email
to look at the new patch set (#2).
Change subject: mb/google/myst: Update PCIe romstage gpios
......................................................................
mb/google/myst: Update PCIe romstage gpios
Update PCIe GPIOs during rom stage to properly initialize the
PCIe devices and allow the NVMe/eMMC to be properly detected.
BUG=b:284213391
TEST=Boot to OS
Change-Id: I24ad6c1addedb414afade2512b6628022d000a47
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
---
M src/mainboard/google/myst/port_descriptors.c
M src/mainboard/google/myst/variants/baseboard/gpio.c
2 files changed, 6 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/75699/2
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Change subject: mb/google/myst: Update PCIe romstage gpios
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/75699/comment/cd0c9e16_c8c9fee3 :
PS1, Line 203: /* SSD_AUX_RESET */
Recommend doing the same for SD as well since that also needs to be brought out of reset before PCIe link training.
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