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Change subject: mb/google/nissa/var/yavilla: Enable wifi SAR
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Good to see get_wifi_sar_fw_config_filename helpful :p
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Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74713?usp=email )
Change subject: mb/google/brya/var/vell: Generate SPD ID for supported memory part
......................................................................
mb/google/brya/var/vell: Generate SPD ID for supported memory part
Add new memory parts
DRAM Part Name ID to assign
Hynix H58G66AK6BX070 3 (0011)
Hynix H9JCNNNFA5MLYR-N6E 4 (0100)
Micron MT62F2G32D8DR-031 WT:B 4 (0100)
BUG=b:279325772
BRANCH=firmware-brya-14505.B
TEST=run part_id_gen to generate SPD id
Change-Id: I2e6a916de08e7c05e95909d2b69bc839d13192d9
Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74713
Reviewed-by: YH Lin <yueherngl(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Derek Huang <derekhuang(a)google.com>
---
M src/mainboard/google/brya/variants/vell/memory/Makefile.inc
M src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt
3 files changed, 8 insertions(+), 0 deletions(-)
Approvals:
Shon Wang: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
YH Lin: Looks good to me, but someone else must approve
Derek Huang: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/vell/memory/Makefile.inc b/src/mainboard/google/brya/variants/vell/memory/Makefile.inc
index 012e70e..383e5aa 100644
--- a/src/mainboard/google/brya/variants/vell/memory/Makefile.inc
+++ b/src/mainboard/google/brya/variants/vell/memory/Makefile.inc
@@ -7,3 +7,5 @@
SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B
SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B, H9JCNNNCP3MLYR-N6E
SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = H58G56AK6BX069
+SPD_SOURCES += spd/lp5/set-0/spd-6.hex # ID = 3(0b0011) Parts = H58G66AK6BX070
+SPD_SOURCES += spd/lp5/set-0/spd-4.hex # ID = 4(0b0100) Parts = MT62F2G32D8DR-031 WT:B, H9JCNNNFA5MLYR-N6E
diff --git a/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt
index 057bb13..ccca70a 100644
--- a/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/vell/memory/dram_id.generated.txt
@@ -8,3 +8,6 @@
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNCP3MLYR-N6E 1 (0001)
H58G56AK6BX069 2 (0010)
+H58G66AK6BX070 3 (0011)
+MT62F2G32D8DR-031 WT:B 4 (0100)
+H9JCNNNFA5MLYR-N6E 4 (0100)
diff --git a/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt
index 62769f1e..6bc68db 100644
--- a/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/vell/memory/mem_parts_used.txt
@@ -13,3 +13,6 @@
MT62F1G32D4DR-031 WT:B
H9JCNNNCP3MLYR-N6E
H58G56AK6BX069
+H58G66AK6BX070
+MT62F2G32D8DR-031 WT:B
+H9JCNNNFA5MLYR-N6E
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Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75605?usp=email )
Change subject: mb/google/dedede/var/taranza: Update memory part and generate SPD ID
......................................................................
mb/google/dedede/var/taranza: Update memory part and generate SPD ID
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts.
The memory parts being added are:
1. K4U6E3S4AB-MGCL
2. K4UBE3D4AB-MGCL
BUG=b:285504022
BRANCH=dedede
TEST=build
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com>
Change-Id: I87a4dcdb6196c3ca7bed4b5c1bc654297339c16d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75605
Reviewed-by: Ricky Chang <rickytlchang(a)google.com>
Reviewed-by: Derek Huang <derekhuang(a)google.com>
Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/dedede/variants/taranza/memory/Makefile.inc
M src/mainboard/google/dedede/variants/taranza/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/taranza/memory/mem_parts_used.txt
3 files changed, 8 insertions(+), 3 deletions(-)
Approvals:
Ricky Chang: Looks good to me, but someone else must approve
David Wu: Looks good to me, approved
build bot (Jenkins): Verified
Sheng-Liang Pan: Looks good to me, but someone else must approve
Derek Huang: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/taranza/memory/Makefile.inc b/src/mainboard/google/dedede/variants/taranza/memory/Makefile.inc
index 43f5136..563fc9a 100644
--- a/src/mainboard/google/dedede/variants/taranza/memory/Makefile.inc
+++ b/src/mainboard/google/dedede/variants/taranza/memory/Makefile.inc
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
-# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/taranza/memory/ src/mainboard/google/dedede/variants/taranza/memory/mem_parts_used.txt
+# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/taranza/memory/ src/mainboard/google/dedede/variants/taranza/memory/mem_parts_used.txt
SPD_SOURCES =
-SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B
+SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, K4U6E3S4AB-MGCL
+SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AB-MGCL
diff --git a/src/mainboard/google/dedede/variants/taranza/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/taranza/memory/dram_id.generated.txt
index c3e8e42..e77699e 100644
--- a/src/mainboard/google/dedede/variants/taranza/memory/dram_id.generated.txt
+++ b/src/mainboard/google/dedede/variants/taranza/memory/dram_id.generated.txt
@@ -1,7 +1,9 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
-# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/taranza/memory/ src/mainboard/google/dedede/variants/taranza/memory/mem_parts_used.txt
+# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/taranza/memory/ src/mainboard/google/dedede/variants/taranza/memory/mem_parts_used.txt
DRAM Part Name ID to assign
MT53E512M32D1NP-046 WT:B 0 (0000)
+K4U6E3S4AB-MGCL 0 (0000)
+K4UBE3D4AB-MGCL 1 (0001)
diff --git a/src/mainboard/google/dedede/variants/taranza/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/taranza/memory/mem_parts_used.txt
index b85681b..529f52d4 100644
--- a/src/mainboard/google/dedede/variants/taranza/memory/mem_parts_used.txt
+++ b/src/mainboard/google/dedede/variants/taranza/memory/mem_parts_used.txt
@@ -10,3 +10,5 @@
# Part Name
MT53E512M32D1NP-046 WT:B
+K4U6E3S4AB-MGCL
+K4UBE3D4AB-MGCL
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Change subject: soc/amd/smm: Sanity check the SMM TSEG size
......................................................................
Patch Set 7: Code-Review+1
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Change subject: mb/google/rex/variants/ovis: Add SPI configuration
......................................................................
Patch Set 5: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75577/comment/b8f61afc_c39d254e :
PS5, Line 7: mb/google/rex/variants/ovis: Add SPI configuration
Enable EC in device tree?
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Change subject: mb/google/rex/variants/ovis: Add USB and TCSS configuration
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
TCSS 0/1 use dma0, TCSS 2/3 use dma1. You can find this in Intel doc.
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Change subject: mb/intel/mtlrvp: Add CPU power limit values
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Patch Set 1: Code-Review+2
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Change subject: soc/amd/*/root_complex: reserve IOMMU MMIO area
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
Patchset:
PS4:
btw, quick look read_resources could be common code.
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Change subject: mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAM
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