coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[master]: soc/intel/jasperlake: Add per-SKU power limits
by Sumeet R Pawnikar (Code Review) 09 Jun '23

09 Jun '23

Attention is currently required from: ChiaLing, Paul Menzel, Reka Norman, Ryan Lin, Zhuohao Lee. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75679?usp=email ) Change subject: soc/intel/jasperlake: Add per-SKU power limits ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/jasperlake/systemagent.c: https://review.coreboot.org/c/coreboot/+/75679/comment/a7ad7a80_f97b69ea : PS5, Line 71: /* Choose power limits configuration based on the CPU SA PCI ID and : * CPU TDP value. */ Use the common code as per this CL https://review.coreboot.org/c/coreboot/+/74620 functionality, instead of adding this code here. -- To view, visit https://review.coreboot.org/c/coreboot/+/75679?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd Gerrit-Change-Number: 75679 Gerrit-PatchSet: 5 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Fri, 09 Jun 2023 07:30:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mainboard/google: move tpm_tis to AMD common code
by Eric Lai (Code Review) 09 Jun '23

09 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Grzegorz Bernacki, Jason Glenesk, Jason Nien, Jon Murphy, Martin Roth, Matt DeVillier, Raul Rangel. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75621?usp=email ) Change subject: mainboard/google: move tpm_tis to AMD common code ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/gpio/tpm_tis.c: https://review.coreboot.org/c/coreboot/+/75621/comment/798d34cf_9d119fd7 : PS1, Line 11: if (CONFIG(BOARD_GOOGLE_NIPPERKIN) && board_id() == 1) > Ah, so add a new Kconfig (DEFAULT_TPM_TIS_IRQ_STATUS) that is set to y when `CONFIG_TPM_GOOGLE`, but […] you can provide board level call back and return CONFIG_TPM_TIS_INTERRUPT, than you still have change to override by __weak function. -- To view, visit https://review.coreboot.org/c/coreboot/+/75621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8 Gerrit-Change-Number: 75621 Gerrit-PatchSet: 1 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 09 Jun 2023 07:28:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Grzegorz Bernacki Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/wwan/fm: Fix format string vulnerability with snprintf
by Subrata Banik (Code Review) 09 Jun '23

09 Jun '23

Attention is currently required from: Cliff Huang, Hannah Williams, Jamie Ryu, Paul Menzel, Tarun Tuli, Wonkyu Kim. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75733?usp=email ) Change subject: drivers/wwan/fm: Fix format string vulnerability with snprintf ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75733?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6b7d70c0b2b86d0918e58348dccd206a7ee9193 Gerrit-Change-Number: 75733 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 09 Jun 2023 07:23:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Add CPU power limit values
by Subrata Banik (Code Review) 09 Jun '23

09 Jun '23

Attention is currently required from: Kapil Porwal, Sumeet R Pawnikar, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75730?usp=email ) Change subject: mb/intel/mtlrvp: Add CPU power limit values ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11bc17f25d4880562d016e29f81e37e068bb6757 Gerrit-Change-Number: 75730 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Fri, 09 Jun 2023 07:23:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: arch/x86/smbios: Add weak function for BIOS Vendor in SMBIOS Type0
by Yiwei Tang (Code Review) 09 Jun '23

09 Jun '23

Yiwei Tang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75737?usp=email ) Change subject: arch/x86/smbios: Add weak function for BIOS Vendor in SMBIOS Type0 ...................................................................... arch/x86/smbios: Add weak function for BIOS Vendor in SMBIOS Type0 Change-Id: I6dfcca338ffc48b150c966b9aefcefe928704d24 Signed-off-by: Yiwei Tang <tangyiwei.2022(a)bytedance.com> --- M src/arch/x86/smbios.c M src/arch/x86/smbios_defaults.c M src/include/smbios.h 3 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/75737/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 1ec0ad2..46096af 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -356,7 +356,7 @@ struct smbios_type0 *t = smbios_carve_table(*current, SMBIOS_BIOS_INFORMATION, sizeof(*t), handle); - t->vendor = smbios_add_string(t->eos, "coreboot"); + t->vendor = smbios_add_string(t->eos, get_bios_vendor()); t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date); if (CONFIG(CHROMEOS_NVS)) { diff --git a/src/arch/x86/smbios_defaults.c b/src/arch/x86/smbios_defaults.c index 8b62ebb..9738c22 100644 --- a/src/arch/x86/smbios_defaults.c +++ b/src/arch/x86/smbios_defaults.c @@ -162,3 +162,8 @@ { return 1; } + +__weak const char *get_bios_vendor(void) +{ + return "coreboot"; +} diff --git a/src/include/smbios.h b/src/include/smbios.h index 446652c..c06d67e 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -79,6 +79,7 @@ const char *smbios_processor_serial_number(void); u8 smbios_chassis_power_cords(void); +const char *get_bios_vendor(void); /* This string could be filled late in payload. */ void smbios_type0_bios_version(uintptr_t address); -- To view, visit https://review.coreboot.org/c/coreboot/+/75737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6dfcca338ffc48b150c966b9aefcefe928704d24 Gerrit-Change-Number: 75737 Gerrit-PatchSet: 1 Gerrit-Owner: Yiwei Tang Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: soc/intel/meteorlake: Add support for crashlog
by Eric Lai (Code Review) 09 Jun '23

09 Jun '23

Attention is currently required from: Kane Chen, Kapil Porwal, Paul Menzel, Pratikkumar V Prajapati, Subrata Banik, Tarun Tuli. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74769?usp=email ) Change subject: soc/intel/meteorlake: Add support for crashlog ...................................................................... Patch Set 23: (1 comment) File src/soc/intel/meteorlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/74769/comment/e639316b_e8b8a2ff : PS23, Line 14: static bool m_pmc_crashLog_support; Better create a struct for support,present,size ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/74769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Gerrit-Change-Number: 74769 Gerrit-PatchSet: 23 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Fri, 09 Jun 2023 07:21:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex/variants/ovis: Add SPI configuration
by Subrata Banik (Code Review) 09 Jun '23

09 Jun '23

Attention is currently required from: Eric Lai, Jakub Czapiga, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75577?usp=email ) Change subject: mb/google/rex/variants/ovis: Add SPI configuration ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75577/comment/3a129916_775a50e5 : PS5, Line 7: mb/google/rex/variants/ovis: Add SPI configuration > Enable EC in device tree? +2, should be EC in commit msg -- To view, visit https://review.coreboot.org/c/coreboot/+/75577?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f3fa6543a4cec8c2562196105f17fbc7831bab7 Gerrit-Change-Number: 75577 Gerrit-PatchSet: 5 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 09 Jun 2023 07:19:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/nissa/var/uldren: Modify WWAN power sequence
by Eric Lai (Code Review) 09 Jun '23

09 Jun '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75690?usp=email ) Change subject: mb/google/nissa/var/uldren: Modify WWAN power sequence ...................................................................... mb/google/nissa/var/uldren: Modify WWAN power sequence Follow spec[1] to modify WWAN power sequence. The WWAN power sequence of warm reset is fail. The correct sequence is WWAN_EN should keep high when doing warm reset. Set GPP_D6 to PWROK which is not to do PAD reset when warm reset. [1]: [JDB10] FC ADL-N_WWAN sequence_FM101-GL SDX12 Power Timing Review_V1.6_20230602.xlsx BUG=b:285065375 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot chromeos-bootimage 2. power sequence meets spec. Change-Id: If59630dbd10e971c91e01f33a657c01d857bc0b9 Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75690 Reviewed-by: Derek Huang <derekhuang(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/uldren/gpio.c 1 file changed, 1 insertion(+), 3 deletions(-) Approvals: Derek Huang: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/uldren/gpio.c b/src/mainboard/google/brya/variants/uldren/gpio.c index c0c43814..0ea14cd 100644 --- a/src/mainboard/google/brya/variants/uldren/gpio.c +++ b/src/mainboard/google/brya/variants/uldren/gpio.c @@ -20,7 +20,7 @@ /* C1 : SMBDA==> TCHSCR_RST_L */ PAD_CFG_GPO(GPP_C1, 1, DEEP), /* D6 : SRCCLKREQ1# ==> WWAN_EN */ - PAD_CFG_GPO(GPP_D6, 1, DEEP), + PAD_CFG_GPO(GPP_D6, 1, PWROK), /* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), /* D8 : SRCCLKREQ3# ==> NC */ @@ -61,8 +61,6 @@ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B15 : HP_RST_ODL */ PAD_CFG_GPO(GPP_B15, 0, DEEP), - /* D6 : SRCCLKREQ1# ==> WWAN_EN */ - PAD_CFG_GPO(GPP_D6, 1, DEEP), /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), /* F12 : GSXDOUT ==> WWAN_RST_L */ -- To view, visit https://review.coreboot.org/c/coreboot/+/75690?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If59630dbd10e971c91e01f33a657c01d857bc0b9 Gerrit-Change-Number: 75690 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: src/arch/x86/smbios.c: Change smbios_fill_dimm_serial_number function...
by Yiwei Tang (Code Review) 09 Jun '23

09 Jun '23

Attention is currently required from: lichenchen.carl. Hello lichenchen.carl, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/75736?usp=email to review the following change. Change subject: src/arch/x86/smbios.c: Change smbios_fill_dimm_serial_number function to weak ...................................................................... src/arch/x86/smbios.c: Change smbios_fill_dimm_serial_number function to weak Move smbios_fill_dimm_serial_number function from smbios.c to smbios_defaults.c with __weak.In order to allow ODM override this field. Change-Id: Icc28a56a577f98a2974407175783e32a1e234f86 Signed-off-by: lichenchen.carl <lichenchen.carl(a)bytedance.com> Signed-off-by: Yiwei Tang <tangyiwei.2022(a)bytedance.com> --- M src/arch/x86/smbios.c M src/arch/x86/smbios_defaults.c M src/include/smbios.h 3 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/75736/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 1ec0ad2..8a8b882 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -207,18 +207,6 @@ } } -/* Encodes the SPD serial number into hex */ -static void smbios_fill_dimm_serial_number(const struct dimm_info *dimm, - struct smbios_type17 *t) -{ - char serial[9]; - - snprintf(serial, sizeof(serial), "%02hhx%02hhx%02hhx%02hhx", - dimm->serial[0], dimm->serial[1], dimm->serial[2], dimm->serial[3]); - - t->serial_number = smbios_add_string(t->eos, serial); -} - static int create_smbios_type17_for_dimm(struct dimm_info *dimm, unsigned long *current, int *handle, int type16_handle) diff --git a/src/arch/x86/smbios_defaults.c b/src/arch/x86/smbios_defaults.c index 8b62ebb..dc166b2 100644 --- a/src/arch/x86/smbios_defaults.c +++ b/src/arch/x86/smbios_defaults.c @@ -27,6 +27,16 @@ t->asset_tag = smbios_add_string(t->eos, buf); } +__weak void smbios_fill_dimm_serial_number(const struct dimm_info *dimm, struct smbios_type17 *t) +{ + char serial[9]; + + snprintf(serial, sizeof(serial), "%02hhx%02hhx%02hhx%02hhx", + dimm->serial[0], dimm->serial[1], dimm->serial[2], dimm->serial[3]); + + t->serial_number = smbios_add_string(t->eos, serial); +} + __weak smbios_wakeup_type smbios_system_wakeup_type(void) { return SMBIOS_WAKEUP_TYPE_RESERVED; diff --git a/src/include/smbios.h b/src/include/smbios.h index 446652c..c42cabb 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -1212,6 +1212,8 @@ void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t); +void smbios_fill_dimm_serial_number(const struct dimm_info *dimm, + struct smbios_type17 *t); void smbios_fill_dimm_asset_tag(const struct dimm_info *dimm, struct smbios_type17 *t); void smbios_fill_dimm_locator(const struct dimm_info *dimm, -- To view, visit https://review.coreboot.org/c/coreboot/+/75736?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc28a56a577f98a2974407175783e32a1e234f86 Gerrit-Change-Number: 75736 Gerrit-PatchSet: 1 Gerrit-Owner: Yiwei Tang Gerrit-Reviewer: lichenchen.carl <lichenchen.carl(a)bytedance.com> Gerrit-Attention: lichenchen.carl <lichenchen.carl(a)bytedance.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/nissa/var/yavilla: Enable wifi SAR
by Eric Lai (Code Review) 09 Jun '23

09 Jun '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75673?usp=email ) Change subject: mb/google/nissa/var/yavilla: Enable wifi SAR ...................................................................... mb/google/nissa/var/yavilla: Enable wifi SAR Enable wifi sar function for yavilla/yavilly/yavijo. Use the fw_config to separate SAR setting for different wifi card. BUG=b:286141046 BRANCH=firmware-nissa-15217.B TEST=build, enabled iwlwifi debug, and check dmesg Change-Id: I1bd111a734a250df49535a07ef056d5b68fccb33 Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75673 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Derek Huang <derekhuang(a)google.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/yavilla/overridetree.cb M src/mainboard/google/brya/variants/yavilla/variant.c 3 files changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Derek Huang: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 44c1156..ceac90e 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -378,6 +378,7 @@ select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_INTEL_MIPI_CAMERA select HAVE_WWAN_POWER_SEQUENCE + select CHROMEOS_WIFI_SAR if CHROMEOS config BOARD_GOOGLE_GOTHRAX bool "-> Gothrax" diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb index 6e6e0a9..ede4e54 100644 --- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb +++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb @@ -28,6 +28,15 @@ option MB_1C 0 option MB_1C_2A 1 end + field WIFI_SAR_ID2 16 19 + option INTEL_YAVILLA_LTE 0 + option INTEL_YAVILLA_WIFI 1 + option INTEL_YAVILLY_LTE 2 + option INTEL_YAVILLY_WIFI 3 + option INTEL_YAVIJO_LTE 4 + option INTEL_YAVIJO_WIFI 5 + option UNUSED 15 + end end chip soc/intel/alderlake diff --git a/src/mainboard/google/brya/variants/yavilla/variant.c b/src/mainboard/google/brya/variants/yavilla/variant.c index 60a7c79..9140eb0 100644 --- a/src/mainboard/google/brya/variants/yavilla/variant.c +++ b/src/mainboard/google/brya/variants/yavilla/variant.c @@ -4,6 +4,7 @@ #include <boardid.h> #include <device/device.h> #include <fw_config.h> +#include <sar.h> void variant_devtree_update(void) { @@ -27,3 +28,8 @@ ish->enabled = 0; } } + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID2)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/75673?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bd111a734a250df49535a07ef056d5b68fccb33 Gerrit-Change-Number: 75673 Gerrit-PatchSet: 3 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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