coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: Delete unused variables
by Ziang Wang (Code Review) 09 Jun '23

09 Jun '23

Ziang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75742?usp=email ) Change subject: Delete unused variables ...................................................................... Delete unused variables Change-Id: I6a96e6549abfdfae67293340943014e8cfb602fe Signed-off-by: Ziang Wang <ziang.wang(a)intel.com> --- M src/drivers/ipmi/ipmi_kcs_ops.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/75742/1 diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 9bf3e14..53d1468 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -65,7 +65,6 @@ uint32_t man_id = 0, prod_id = 0; struct drivers_ipmi_config *conf = dev->chip_info; const struct gpio_operations *gpio_ops; - struct ipmi_selftest_rsp selftestrsp = {0}; int retries = 10; if (!conf) { -- To view, visit https://review.coreboot.org/c/coreboot/+/75742?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a96e6549abfdfae67293340943014e8cfb602fe Gerrit-Change-Number: 75742 Gerrit-PatchSet: 1 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/intel/spr-sp: Remove HWP related settings
by Ziang Wang (Code Review) 09 Jun '23

09 Jun '23

Ziang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75741?usp=email ) Change subject: soc/intel/spr-sp: Remove HWP related settings ...................................................................... soc/intel/spr-sp: Remove HWP related settings HWP feature can be set via 'CpuPmProcessorHWPMEnable' UPD option in FSP-S, so related manipulations in coreboot are being removed. Change-Id: Ic4ff63cbff0dffb4cd65fdfa814eda85964130ee Signed-off-by: wanghao11 <wanghao11(a)inspur.com> Signed-off-by: Ziang Wang <ziang.wang(a)intel.com> --- M src/soc/intel/xeon_sp/spr/cpu.c 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/75741/1 diff --git a/src/soc/intel/xeon_sp/spr/cpu.c b/src/soc/intel/xeon_sp/spr/cpu.c index 2ed8e22..556ecef 100644 --- a/src/soc/intel/xeon_sp/spr/cpu.c +++ b/src/soc/intel/xeon_sp/spr/cpu.c @@ -122,14 +122,15 @@ wrmsr(PACKAGE_RAPL_LIMIT, msr); /* - * Set HWP base feature, EPP reg enumeration, lock thermal and msr + * HWP feature can be set via CpuPmProcessorHWPMEnable UPD option during FSP-S stage, + * so programming of MSR_MISC_PWR_MGMT and LOCK_THERM_INT is skipped here. + * If msr MSR_MISC_PWR_MGMT hasn't been locked, lock it here. * This is package level MSR. Need to check if it updates correctly on * multi-socket platform. */ msr = rdmsr(MSR_MISC_PWR_MGMT); if (!(msr.lo & LOCK_MISC_PWR_MGMT_MSR)) { /* if already locked skip update */ - msr.lo = (HWP_ENUM_ENABLE | HWP_EPP_ENUM_ENABLE | LOCK_MISC_PWR_MGMT_MSR - | LOCK_THERM_INT); + msr.lo |= LOCK_MISC_PWR_MGMT_MSR; wrmsr(MSR_MISC_PWR_MGMT, msr); } -- To view, visit https://review.coreboot.org/c/coreboot/+/75741?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4ff63cbff0dffb4cd65fdfa814eda85964130ee Gerrit-Change-Number: 75741 Gerrit-PatchSet: 1 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/nissa/var/joxer: Configure the external V1p05/Vnn/VnnSx rails
by Baieswara Reddy Sagili (Code Review) 09 Jun '23

09 Jun '23

Attention is currently required from: Derek Huang, Eric Lai, Felix Held, Henry Sun, Kangheui Won, Mark Hsieh, Paul Menzel, Shou-Chieh Hsu, Sumeet R Pawnikar, Tarun Tuli. Baieswara Reddy Sagili has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75662?usp=email ) Change subject: mb/google/nissa/var/joxer: Configure the external V1p05/Vnn/VnnSx rails ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75662?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78d2a885d577f6c1a89ab74c0da7b6544322c0d7 Gerrit-Change-Number: 75662 Gerrit-PatchSet: 5 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 09 Jun 2023 08:29:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/joxer: Configure the external V1p05/Vnn/VnnSx rails
by Mark Hsieh (Code Review) 09 Jun '23

09 Jun '23

Attention is currently required from: Baieswara Reddy Sagili, Derek Huang, Eric Lai, Felix Held, Henry Sun, Kangheui Won, Paul Menzel, Shou-Chieh Hsu, Sumeet R Pawnikar, Tarun Tuli. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75662?usp=email ) Change subject: mb/google/nissa/var/joxer: Configure the external V1p05/Vnn/VnnSx rails ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75662/comment/3bf9301e_c18707c7 : PS3, Line 7: mb/google/nissa > please add /var/joxer. and remove it from title. Updated. File src/mainboard/google/brya/variants/joxer/overridetree.cb: https://review.coreboot.org/c/coreboot/+/75662/comment/3d4de043_5b78ad99 : PS3, Line 18: .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, > External V1P05 rail should be disabled during S0. […] Updated. -- To view, visit https://review.coreboot.org/c/coreboot/+/75662?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78d2a885d577f6c1a89ab74c0da7b6544322c0d7 Gerrit-Change-Number: 75662 Gerrit-PatchSet: 5 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 09 Jun 2023 08:14:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/xeon_sp/spr: Fix memory max capacity per processor
by Lean Sheng Tan (Code Review) 09 Jun '23

09 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Singer, Johnny Lin, Nico Huber, Paul Menzel, Tim Chu, Ziang Wang. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75740?usp=email ) Change subject: soc/intel/xeon_sp/spr: Fix memory max capacity per processor ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767 Gerrit-Change-Number: 75740 Gerrit-PatchSet: 1 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 09 Jun 2023 08:13:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/xeon_sp/spr: Fix memory max capacity per processor
by Ziang Wang (Code Review) 09 Jun '23

09 Jun '23

Ziang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75740?usp=email ) Change subject: soc/intel/xeon_sp/spr: Fix memory max capacity per processor ...................................................................... soc/intel/xeon_sp/spr: Fix memory max capacity per processor The capacity shall be 6*TiB per processor. Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767 Signed-off-by: wanghao11 <wanghao11(a)inspur.com> Signed-off-by: Ziang Wang <ziang.wang(a)intel.com> --- M src/soc/intel/xeon_sp/spr/romstage.c 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/75740/1 diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index fef4d94..62b6212 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -271,8 +271,12 @@ return; } memset(mem_info, 0, sizeof(*mem_info)); - /* According to EDS doc#611488, it's 4 TB per processor. */ - mem_info->max_capacity_mib = 4 * MiB * CONFIG_MAX_SOCKET; + /* + * According to EDS doc#611488, it's 6 TB per processor + * Max Capacity: (x8 256 GB 16 Gb 3DS DDR5) and (x8 512 GB Intel® Optane™ + * Persistent Memory 300 Series mapped as memory) per Socket + */ + mem_info->max_capacity_mib = 6 * MiB * CONFIG_MAX_SOCKET; mem_info->number_of_devices = CONFIG_DIMM_MAX; mem_info->ecc_type = get_error_correction_type(hob->RasModesEnabled); dimm_max = ARRAY_SIZE(mem_info->dimm); -- To view, visit https://review.coreboot.org/c/coreboot/+/75740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767 Gerrit-Change-Number: 75740 Gerrit-PatchSet: 1 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/nissa/var/joxer: Configure the external V1p05/Vnn/VnnSx rails
by Mark Hsieh (Code Review) 09 Jun '23

09 Jun '23

Attention is currently required from: Derek Huang, Eric Lai, Felix Held, Henry Sun, Kangheui Won, Mark Hsieh, Paul Menzel, Shou-Chieh Hsu, Sumeet R Pawnikar, Tarun Tuli. Hello Baieswara Reddy Sagili, Derek Huang, Eric Lai, Felix Held, Henry Sun, Kangheui Won, Paul Menzel, Reka Norman, Shou-Chieh Hsu, Sumeet R Pawnikar, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75662?usp=email to look at the new patch set (#5). Change subject: mb/google/nissa/var/joxer: Configure the external V1p05/Vnn/VnnSx rails ...................................................................... mb/google/nissa/var/joxer: Configure the external V1p05/Vnn/VnnSx rails This patch configures external V1p05/Vnn/VnnSx rails for Joxer to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. Kit: 646929 - ADL N Platform Design Guide BUG=b:285477026 TEST=Verified all the UPD values are updated with these configs. Signed-off-by: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Change-Id: I78d2a885d577f6c1a89ab74c0da7b6544322c0d7 --- M src/mainboard/google/brya/variants/joxer/overridetree.cb 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/75662/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/75662?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78d2a885d577f6c1a89ab74c0da7b6544322c0d7 Gerrit-Change-Number: 75662 Gerrit-PatchSet: 5 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: soc/intel/xeon_sp: Fix HEST table length
by Lean Sheng Tan (Code Review) 09 Jun '23

09 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Jeff Li, Johnny Lin, Nico Huber, Paul Menzel, Tim Chu, Yiwei Tang, Ziang Wang. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75738?usp=email ) Change subject: soc/intel/xeon_sp: Fix HEST table length ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ff1e8e24612b7356772d582ff9a7e53863419db Gerrit-Change-Number: 75738 Gerrit-PatchSet: 1 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeff Li <lijinfeng01(a)inspur.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Yiwei Tang Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yiwei Tang Gerrit-Attention: Jeff Li <lijinfeng01(a)inspur.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 09 Jun 2023 08:07:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/ipmi: retry ipmi_get_device_id in ipmi_kcs_init
by Ziang Wang (Code Review) 09 Jun '23

09 Jun '23

Attention is currently required from: Lean Sheng Tan, Yiwei Tang. Ziang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75739?usp=email ) Change subject: drivers/ipmi: retry ipmi_get_device_id in ipmi_kcs_init ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hi, this is a change from spr-sp repo, original post if available: https://review.coreboot.org/c/coreboot-spr-sp/+/67947 -- To view, visit https://review.coreboot.org/c/coreboot/+/75739?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b2b15170c3ac9785b6e1cc7f93738f7badc7435 Gerrit-Change-Number: 75739 Gerrit-PatchSet: 1 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Yiwei Tang Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Yiwei Tang Gerrit-Comment-Date: Fri, 09 Jun 2023 08:06:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/ipmi: retry ipmi_get_device_id in ipmi_kcs_init
by Ziang Wang (Code Review) 09 Jun '23

09 Jun '23

Ziang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75739?usp=email ) Change subject: drivers/ipmi: retry ipmi_get_device_id in ipmi_kcs_init ...................................................................... drivers/ipmi: retry ipmi_get_device_id in ipmi_kcs_init Based on our test, there is probability that ipmi init fails in DC Cycle stress test, so we add this retry mechanism. Change-Id: I2b2b15170c3ac9785b6e1cc7f93738f7badc7435 Signed-off-by: wanghao11 <wanghao11(a)inspur.com> Signed-off-by: Ziang Wang <ziang.wang(a)intel.com> --- M src/drivers/ipmi/ipmi_kcs_ops.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/75739/1 diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 2e5378f..9bf3e14 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -65,6 +65,8 @@ uint32_t man_id = 0, prod_id = 0; struct drivers_ipmi_config *conf = dev->chip_info; const struct gpio_operations *gpio_ops; + struct ipmi_selftest_rsp selftestrsp = {0}; + int retries = 10; if (!conf) { printk(BIOS_WARNING, "IPMI: chip_info is missing! Skip init.\n"); @@ -127,6 +129,22 @@ return; } + while (ipmi_get_device_id(dev, &rsp)) { + retries--; + printk(BIOS_DEBUG, "IPMI: BMC does not respond to get device id, %d retries left\n", + retries); + if (retries == 0) { + dev->enabled = 0; + break; + } + mdelay(1000); + } + + if (!dev->enabled) { + printk(BIOS_ERR, "IPMI: BMC does not respond to get device id even after retries.\n"); + return; + } + /* Queried the IPMI revision from BMC */ ipmi_revision_minor = IPMI_IPMI_VERSION_MINOR(rsp.ipmi_version); ipmi_revision_major = IPMI_IPMI_VERSION_MAJOR(rsp.ipmi_version); -- To view, visit https://review.coreboot.org/c/coreboot/+/75739?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b2b15170c3ac9785b6e1cc7f93738f7badc7435 Gerrit-Change-Number: 75739 Gerrit-PatchSet: 1 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2023