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Change subject: mb/google/nissa: Configure the external V1p05/Vnn/VnnSx rails for joxer
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75662/comment/24b06e2e_7532283e :
PS3, Line 7: mb/google/nissa
please add /var/joxer. and remove it from title.
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Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75722/comment/98acaae0_05b47c97 :
PS5, Line 19: The board boots to Linux 5.10 with all 192 cores available.
: All PCIe devices 64 and DIMMS are working.
What does `sudo dmesg --level alert,crit,err,warn` show?
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Change subject: mb/google/rex/variants/ovis: Add basic DTT
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75580/comment/a7a28d52_722e1c7a :
PS5, Line 8:
Please add a line to the commit message body.
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Change subject: mb/google/rex/variants/ovis: Add basic DTT
......................................................................
Patch Set 5: Code-Review+2
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Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs
......................................................................
Patch Set 5:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75722/comment/e01c0cff_951e09d4 :
PS3, Line 4: TangYiwei
> Please add a space, and put the surname at the end. […]
Done
https://review.coreboot.org/c/coreboot/+/75722/comment/1a7923a1_1ddb1087 :
PS3, Line 9: bd_egs
> In `src/mainboard/bytedance/bd_egs/board_info.txt` it’s named Eaglestream. […]
Eaglestream is intel platform. Change our board_info.txt board name.
https://review.coreboot.org/c/coreboot/+/75722/comment/53220395_238937af :
PS3, Line 11:
> Please look at commit 30e743e7cc7f (mb/ibm: Add 4 SPR sockets server board IBM SBP1), Ie21c744224e8d […]
Done
https://review.coreboot.org/c/coreboot/+/75722/comment/bc31ccb7_0ed43015 :
PS3, Line 14: Yuuka_Kazami <caolong01(a)inspur.com>
: Co-authored-by: wanghao11 <wanghao11(a)inspur.com>
: Co-authored-by: lanchenyu <lanchenyu(a)inspur.com>
: Co-authored-by: laykong <lay.kong(a)intel.com>
: Co-authored-by: kehong-intel <kehong.chen(a)intel.com>
: Co-authored-by: ziang <ziang.wang(a)intel.com>
: Co-authored-by: weidong <weidong.wd(a)bytedance.com>
: Co-authored-by: lichenchen.carl
> It’d be great if you spelled the full names as the other names.
Done
File src/mainboard/bytedance/bd_egs/bootblock.c:
https://review.coreboot.org/c/coreboot/+/75722/comment/22b0dedd_de04ce86 :
PS3, Line 25: * For ArcherCity CRB, only SUART1 is used.
> Looks copy-pasted.
Done
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Change subject: util: Use common ARRAY_SIZE define
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS2:
> had a brief discussion about this in the last coreboot leadership meeting and the idea of commonlib […]
Great, thanks for confirmation!
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Hello Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nill Ge, Patrick Rudolph, Paul Menzel, build bot (Jenkins), niehaitao(a)bytedance.com,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75722?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Code-Review+1 by Jonathan Zhang, Verified+1 by build bot (Jenkins)
Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs
......................................................................
mb/bytedance: Add 2 SPR sockets server board bd_egs
Bytedance bd_egs is a dual socket MB with Intel Sapphire Rapids
Scalable Processor chipset.
It's utilising:
- 2 SPR sockets
- Max 32 DIMMs
- 33x CPU PCIe slots
- AST2600 for VGA and BMC remote management
Test:
The board boots to Linux 5.10 with all 192 cores available.
All PCIe devices 64 and DIMMS are working.
Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d
Co-authored-by: Jinfeng Li <lijinfeng01(a)ieisystem.com>
Co-authored-by: Long Cao <caolong01(a)inspur.com>
Co-authored-by: Hao Wang <wanghao11(a)inspur.com>
Co-authored-by: Chenyu Lan <lanchenyu(a)inspur.com>
Co-authored-by: Lay Kong <lay.kong(a)intel.com>
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Co-authored-by: Dong Wei <weidong.wd(a)bytedance.com>
Co-authored-by: Chenchen Li <lichenchen.carl(a)bytedance.com>
Signed-off-by: Yiwei Tang <tangyiwei.2022(a)bytedance.com>
Reviewed-by: Haitao Nie<niehaitao(a)bytedance.com>
Reviewed-by: Shijian Ge<geshijian(a)bytedance.com>
---
A src/mainboard/bytedance/Kconfig
A src/mainboard/bytedance/Kconfig.name
A src/mainboard/bytedance/bd_egs/Kconfig
A src/mainboard/bytedance/bd_egs/Kconfig.name
A src/mainboard/bytedance/bd_egs/Makefile.inc
A src/mainboard/bytedance/bd_egs/acpi/platform.asl
A src/mainboard/bytedance/bd_egs/board.fmd
A src/mainboard/bytedance/bd_egs/board_info.txt
A src/mainboard/bytedance/bd_egs/bootblock.c
A src/mainboard/bytedance/bd_egs/devicetree.cb
A src/mainboard/bytedance/bd_egs/dsdt.asl
A src/mainboard/bytedance/bd_egs/gpio.c
A src/mainboard/bytedance/bd_egs/gpio.h
A src/mainboard/bytedance/bd_egs/include/sprsp_bd_iio.h
A src/mainboard/bytedance/bd_egs/ramstage.c
A src/mainboard/bytedance/bd_egs/romstage.c
16 files changed, 782 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/75722/4
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Change subject: mb/google/dedede/var/dibbi: Update power limits
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/dedede/variants/dibbi/ramstage.c:
https://review.coreboot.org/c/coreboot/+/75681/comment/103705c9_a7da65c1 :
PS5, Line 15:
Add tab here.
Also, for single line comment use comment format as per above line #14, not // comment.
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Change subject: mb/google/rex/variants/ovis: Add basic DTT
......................................................................
Patch Set 5: Code-Review+2
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