coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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5387 discussions

[XS] Change in coreboot[master]: mb/google/brya/acpi: Turn NV12 enable signal off on GCOFF entry
by Tarun Tuli (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Tarun Tuli. Hello Eran Mitrani, Eric Lai, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75533?usp=email to look at the new patch set (#6). Change subject: mb/google/brya/acpi: Turn NV12 enable signal off on GCOFF entry ...................................................................... mb/google/brya/acpi: Turn NV12 enable signal off on GCOFF entry Properly shutdown NV12 rail in the off sequence (current implementation leaves it asserted). BUG=b:286287940 TEST=NV12 now shuts down on GCOFF entry Change-Id: I7d338fc4a96f119617aff558413a5a9ac44c27d7 Signed-off-by: Tarun Tuli <taruntuli(a)google.com> --- M src/mainboard/google/brya/acpi/power.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/75533/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/75533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d338fc4a96f119617aff558413a5a9ac44c27d7 Gerrit-Change-Number: 75533 Gerrit-PatchSet: 6 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/dedede: Support variant specific power limits
by Paul Menzel (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: ChiaLing, Reka Norman, Ryan Lin, Zhuohao Lee. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75680?usp=email ) Change subject: mb/google/dedede: Support variant specific power limits ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75680/comment/d3f249a6_6a9a8c76 : PS3, Line 11: adapter. Fits on the line above. -- To view, visit https://review.coreboot.org/c/coreboot/+/75680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I583c930379233322c41027805369f81d02000ee7 Gerrit-Change-Number: 75680 Gerrit-PatchSet: 3 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 15:21:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Add PsysPl1 support
by ChiaLing (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Reka Norman, Ryan Lin, Zhuohao Lee. Hello Reka Norman, Ryan Lin, Zhuohao Lee, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75678?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common: Add PsysPl1 support ...................................................................... soc/intel/common: Add PsysPl1 support Set PsysPL1 in set_power_limits in order to increase system performance for no battery design. More power budget for SOC may be released accordingly. BUG=b:281479111 TEST=emerge-dedede coreboot and check PsysPl1 value on DUT Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com> Change-Id: I0b2cf2c90ddef422c121e90edbe79dacb7e29320 --- M src/soc/intel/common/block/include/intelblocks/power_limit.h M src/soc/intel/common/block/power_limit/power_limit.c 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/75678/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75678?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b2cf2c90ddef422c121e90edbe79dacb7e29320 Gerrit-Change-Number: 75678 Gerrit-PatchSet: 2 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: soc/mediatek/common: Disable DRAM scramble by default
by Paul Menzel (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75562?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/mediatek/common: Disable DRAM scramble by default ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75562/comment/7659f00b_8f3593cc : PS3, Line 11: and Sorry, I am having trouble to understand the *and*. Will the feature be enabled in production? (Maybe to get better bug reports?) -- To view, visit https://review.coreboot.org/c/coreboot/+/75562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I109634d811a928e3e6f7f56e706a5b61a52a21ab Gerrit-Change-Number: 75562 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 15:18:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/dedede: Support variant specific power limits
by ChiaLing (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Reka Norman, Ryan Lin, Zhuohao Lee. Hello Reka Norman, Ryan Lin, Zhuohao Lee, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75680?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/dedede: Support variant specific power limits ...................................................................... mb/google/dedede: Support variant specific power limits With newer dedede design, it's required to config corresponding psyspmax, psyspl1, psyspl2, pl1 and pl2 by different kind of adapter. BUG=b:281479111 TEST=emerge-dedede coreboot and check correct register value on DUT Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com> Change-Id: I583c930379233322c41027805369f81d02000ee7 --- M src/mainboard/google/dedede/variants/baseboard/Makefile.inc M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/dedede/variants/baseboard/ramstage.c 3 files changed, 212 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/75680/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/75680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I583c930379233322c41027805369f81d02000ee7 Gerrit-Change-Number: 75680 Gerrit-PatchSet: 3 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/amd/mayan:Enable the DT and M.2 SSD1 PCIE slots
by Fred Reitberger (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Anand Vaikar, Felix Held, Jason Glenesk, Matt DeVillier, Paul Menzel, ritul guru. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74069?usp=email ) Change subject: mb/amd/mayan:Enable the DT and M.2 SSD1 PCIE slots ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74069?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id141e5e55ef6e25722b411975a59c9764b86f624 Gerrit-Change-Number: 74069 Gerrit-PatchSet: 14 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 08 Jun 2023 15:00:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/mediatek/common: Disable DRAM scramble by default
by Hung-Te Lin (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Yidi Lin, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75562?usp=email ) Change subject: soc/mediatek/common: Disable DRAM scramble by default ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75562/comment/dcf672ba_f04e1669 : PS3, Line 16: > This feature only implements on geralt and the corsola branch does not have this config. ah that's right, sorry I forgot. -- To view, visit https://review.coreboot.org/c/coreboot/+/75562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I109634d811a928e3e6f7f56e706a5b61a52a21ab Gerrit-Change-Number: 75562 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 14:48:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/inventec: Add Intel SPR server board Inventec Transformers
by Paul Menzel (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Angel Pons, Annie Chen, Arthur Heymans, David Hendricks, Felix Singer, Jonathan Zhang, Lean Sheng Tan. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75598?usp=email ) Change subject: mb/inventec: Add Intel SPR server board Inventec Transformers ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > @Felix Singer This is just the beginning of supporting Inventec Transformer which is a customer serv […] I sent a message to the mailing list [1] before seeing this comment. Please move the discussion there. [1]: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/CFMG… -- To view, visit https://review.coreboot.org/c/coreboot/+/75598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684 Gerrit-Change-Number: 75598 Gerrit-PatchSet: 5 Gerrit-Owner: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Hung-Wei Chen <Chen.HW(a)inventec.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 14:21:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/inventec: Add Intel SPR server board Inventec Transformers
by Paul Menzel (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Angel Pons, Annie Chen, Arthur Heymans, David Hendricks, Felix Singer, Lean Sheng Tan. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75598?usp=email ) Change subject: mb/inventec: Add Intel SPR server board Inventec Transformers ...................................................................... Patch Set 5: (4 comments) File src/mainboard/inventec/transformers/romstage.c: https://review.coreboot.org/c/coreboot/+/75598/comment/1b84b80b_b322fde4 : PS5, Line 16: void mainboard_ewl_check(void) What is ewl? Please add a comment to the function. https://review.coreboot.org/c/coreboot/+/75598/comment/8c58a42f_6f141327 : PS5, Line 102: selftest result first */ Please align the line correctly. https://review.coreboot.org/c/coreboot/+/75598/comment/0bd02afa_0b7d2b63 : PS5, Line 118: /* Enable - Portions of memory reference code will be skipped */ : /* when possible to increase boot speed on warm boots.*/ : /* Disable - Disables this feature. */ : /* Auto - Sets it to the MRC default setting. */ Please use the multi-line commenting style listed in the coding style. https://review.coreboot.org/c/coreboot/+/75598/comment/ca01ed5b_8bd43ff7 : PS5, Line 142: /* Disable FSP memory train results*/ Please add a space at the end. -- To view, visit https://review.coreboot.org/c/coreboot/+/75598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684 Gerrit-Change-Number: 75598 Gerrit-PatchSet: 5 Gerrit-Owner: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Hung-Wei Chen <Chen.HW(a)inventec.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 14:14:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/inventec: Add Intel SPR server board Inventec Transformers
by Paul Menzel (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Angel Pons, Annie Chen, Arthur Heymans, David Hendricks, Felix Singer, Lean Sheng Tan. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75598?usp=email ) Change subject: mb/inventec: Add Intel SPR server board Inventec Transformers ...................................................................... Patch Set 5: (1 comment) File src/mainboard/inventec/transformers/bootblock.c: https://review.coreboot.org/c/coreboot/+/75598/comment/3d2da4d5_ac12dd97 : PS5, Line 23: * For ArcherCity CRB, only SUART1 is used. This seems copy-pasted. -- To view, visit https://review.coreboot.org/c/coreboot/+/75598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684 Gerrit-Change-Number: 75598 Gerrit-PatchSet: 5 Gerrit-Owner: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Hung-Wei Chen <Chen.HW(a)inventec.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 14:12:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit June 2023