coreboot-gerrit June 2023

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Add CPU power limit values
by Sumeet R Pawnikar (Code Review) 08 Jun '23

08 Jun '23

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75730?usp=email ) Change subject: mb/intel/mtlrvp: Add CPU power limit values ...................................................................... mb/intel/mtlrvp: Add CPU power limit values Add support of variant_devtree_update() function to override devtree settings for variant boards. Also, add CPU power limit values for mtlrvp baseboard. BRANCH=None BUG=None TEST=Built the changes Change-Id: I11bc17f25d4880562d016e29f81e37e068bb6757 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/mainboard.c M src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc A src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c 5 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/75730/1 diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index ea6c6cb..4f4526e 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -17,6 +17,7 @@ select HAVE_ACPI_TABLES select HAVE_SPD_IN_CBFS select MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_METEORLAKE_U_P diff --git a/src/mainboard/intel/mtlrvp/mainboard.c b/src/mainboard/intel/mtlrvp/mainboard.c index 9621294..2e515f7 100644 --- a/src/mainboard/intel/mtlrvp/mainboard.c +++ b/src/mainboard/intel/mtlrvp/mainboard.c @@ -35,6 +35,13 @@ if (CONFIG(EC_GOOGLE_CHROMEEC)) mainboard_ec_init(); + + variant_devtree_update(); +} + +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h index f755ff0..726a617 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h @@ -20,4 +20,7 @@ /* Function to initialize memory params based on variant */ const struct mb_cfg *variant_memory_params(void); +/* Modify devictree settings during ramstage */ +void variant_devtree_update(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc index cc5cdc1..dafb64b 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc @@ -2,3 +2,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c new file mode 100644 index 0000000..aee3d88 --- /dev/null +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> +#include <intelblocks/power_limit.h> + +/* + * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts), + * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) + * Following values are for performance config as per document #640982 + */ +const struct cpu_tdp_power_limits limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_2, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 57000, + .pl2_max_power = 57000, + .pl4_power = 114000 + }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_cpu_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/75730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11bc17f25d4880562d016e29f81e37e068bb6757 Gerrit-Change-Number: 75730 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: acpi: Add a debug option to print out tables in ACPICA compatible hex
by Lean Sheng Tan (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Arthur Heymans, Benjamin Doron, Kyösti Mälkki, Lance Zhao, Paul Menzel, Tim Wawrzynczak. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75677?usp=email ) Change subject: acpi: Add a debug option to print out tables in ACPICA compatible hex ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc Gerrit-Change-Number: 75677 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 14:05:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/bytedance: Add 2 SPR sockets server board bd_egs
by Paul Menzel (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Lean Sheng Tan, Nill Ge, Patrick Rudolph, TangYiwei, niehaitao(a)bytedance.com. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75722?usp=email ) Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75722/comment/18d99305_7e439f56 : PS3, Line 9: bd_egs In `src/mainboard/bytedance/bd_egs/board_info.txt` it’s named Eaglestream. Why not use that? File src/mainboard/bytedance/bd_egs/bootblock.c: https://review.coreboot.org/c/coreboot/+/75722/comment/4860cf99_cd1759e2 : PS3, Line 25: * For ArcherCity CRB, only SUART1 is used. Looks copy-pasted. -- To view, visit https://review.coreboot.org/c/coreboot/+/75722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d Gerrit-Change-Number: 75722 Gerrit-PatchSet: 3 Gerrit-Owner: TangYiwei Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: niehaitao(a)bytedance.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: niehaitao(a)bytedance.com Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Thu, 08 Jun 2023 13:59:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/bytedance: Add 2 SPR sockets server board bd_egs
by Paul Menzel (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Lean Sheng Tan, Nill Ge, Patrick Rudolph, TangYiwei, niehaitao(a)bytedance.com. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75722?usp=email ) Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75722/comment/d964f6ab_52217e60 : PS3, Line 4: TangYiwei Please add a space, and put the surname at the end. (I think this is from the Gerrit configuration/profile.) https://review.coreboot.org/c/coreboot/+/75722/comment/888e08bb_52eba8c9 : PS3, Line 11: Please look at commit 30e743e7cc7f (mb/ibm: Add 4 SPR sockets server board IBM SBP1), Ie21c744224e8d9e5232d63b8366d2981c9575d70 1 how to add a new board, and how to write the commit message. https://review.coreboot.org/c/coreboot/+/75722/comment/560cda75_bcf4abf8 : PS3, Line 14: Yuuka_Kazami <caolong01(a)inspur.com> : Co-authored-by: wanghao11 <wanghao11(a)inspur.com> : Co-authored-by: lanchenyu <lanchenyu(a)inspur.com> : Co-authored-by: laykong <lay.kong(a)intel.com> : Co-authored-by: kehong-intel <kehong.chen(a)intel.com> : Co-authored-by: ziang <ziang.wang(a)intel.com> : Co-authored-by: weidong <weidong.wd(a)bytedance.com> : Co-authored-by: lichenchen.carl It’d be great if you spelled the full names as the other names. Patchset: PS3: Welcome to coreboot and thank you very much for the contribution. -- To view, visit https://review.coreboot.org/c/coreboot/+/75722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d Gerrit-Change-Number: 75722 Gerrit-PatchSet: 3 Gerrit-Owner: TangYiwei Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: niehaitao(a)bytedance.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: niehaitao(a)bytedance.com Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Thu, 08 Jun 2023 13:55:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/inventec: Add Intel SPR server board Inventec Transformers
by Jonathan Zhang (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Angel Pons, Annie Chen, Arthur Heymans, David Hendricks, Felix Singer, Lean Sheng Tan, Paul Menzel. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75598?usp=email ) Change subject: mb/inventec: Add Intel SPR server board Inventec Transformers ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Patchset: PS5: > I compared both mainboards, ArcherCity CRB and yours, and most of it is actually the same. […] @Felix Singer This is just the beginning of supporting Inventec Transformer which is a customer server instead of reference board (Intel ArcherCity CRB). More features will be added to such a customer server over time. So variant may not be the best approach. -- To view, visit https://review.coreboot.org/c/coreboot/+/75598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684 Gerrit-Change-Number: 75598 Gerrit-PatchSet: 5 Gerrit-Owner: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Hung-Wei Chen <Chen.HW(a)inventec.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 13:49:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT
by Nico Huber (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Jeff Daly, Lance Zhao, Matt DeVillier, Sean Rhodes, Tim Wawrzynczak, Vanessa Eusebio. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75729?usp=email ) Change subject: UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75729/comment/07655781_e42859a7 : PS2, Line 28: unknown reason Probably because it meddles with e820. So far a reservation there with the exact same base was enough to make Linux happy, FWIW. File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/75729/comment/9da23d98_019dab31 : PS2, Line 587: struct device *dev = dev_find_path(NULL, DEVICE_PATH_DOMAIN); : assert(dev != NULL); We could also export domain devices to `build/static_devices.h`. OTOH, filtering the right device in the loop device should do too. https://review.coreboot.org/c/coreboot/+/75729/comment/930241f1_4c752edf : PS2, Line 594: 1 Shouldn't this be unique (I'm not sure about the scope)? i.e. not the same as in the static `.asl` files. -- To view, visit https://review.coreboot.org/c/coreboot/+/75729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4 Gerrit-Change-Number: 75729 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 08 Jun 2023 13:46:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/bytedance: Add 2 SPR sockets server board bd_egs
by Jonathan Zhang (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Lean Sheng Tan, Nill Ge, Patrick Rudolph, Paul Menzel, TangYiwei, niehaitao(a)bytedance.com. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75722?usp=email ) Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d Gerrit-Change-Number: 75722 Gerrit-PatchSet: 3 Gerrit-Owner: TangYiwei Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: niehaitao(a)bytedance.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: niehaitao(a)bytedance.com Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Thu, 08 Jun 2023 13:45:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex/var/screebo: Enable touchscreen
by Subrata Banik (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Kapil Porwal, Kun Liu, Rui Zhou, Tarun Tuli, zhongtian wu. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75692?usp=email ) Change subject: mb/google/rex/var/screebo: Enable touchscreen ...................................................................... Patch Set 5: Code-Review+2 (2 comments) Patchset: PS1: > > Sorry, I made a mistake, it is the same screen, but the touch ic is different. […] Acknowledged Patchset: PS5: I hope u can land config.star changes as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/75692?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57d55c5f2621d6fafd53b19d12ecad20271cdbb1 Gerrit-Change-Number: 75692 Gerrit-PatchSet: 5 Gerrit-Owner: zhongtian wu <wuzhongtian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Attention: zhongtian wu <wuzhongtian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 13:39:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT
by Arthur Heymans (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Angel Pons, Felix Held, Jeff Daly, Lance Zhao, Matt DeVillier, Nico Huber, Sean Rhodes, Tim Wawrzynczak, Vanessa Eusebio. Hello Angel Pons, Felix Held, Jeff Daly, Lance Zhao, Matt DeVillier, Nico Huber, Sean Rhodes, Tim Wawrzynczak, Vanessa Eusebio, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75729?usp=email to look at the new patch set (#2). Change subject: UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT ...................................................................... UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT From the Linux documentation (Documentation/PCI/acpi-info.rst): [6] PCI Firmware 3.2, sec 4.1.2: If the operating system does not natively comprehend reserving the MMCFG region, the MMCFG region must be reserved by firmware. The address range reported in the MCFG table or by _CBA method (see Section 4.1.3) must be reserved by declaring a motherboard resource. For most systems, the motherboard resource would appear at the root of the ACPI namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and the resources in this case should not be claimed in the root PCI bus’s _CRS. The resources can optionally be returned in Int15 E820 or EFIGetMemoryMap as reserved memory but must always be reported through ACPI as a motherboard resource. So in order for the OS to use ECAM MMCONF over legacy PCI IO configuration, a PNP0C02 HId device needs to reserve this region. Instead of having this code in each DSDT, add this via SSDT on all platforms with CONFIG_ECAM_MMCONF_SUPPORT. As no AMD platforms has this defined in DSDT this fixes Linux using legacy PCI IO configuration over MMCONF. For an unknown reason Linux only complained about this when it was booted with tianocore. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4 --- M src/acpi/acpi.c M src/northbridge/intel/gm45/acpi/gm45.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/i945/acpi/i945.asl M src/northbridge/intel/ironlake/acpi/ironlake.asl M src/northbridge/intel/pineview/acpi/pineview.asl M src/northbridge/intel/sandybridge/acpi/sandybridge.asl M src/northbridge/intel/x4x/acpi/x4x.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/baytrail/acpi/southcluster.asl M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/denverton_ns/acpi/northcluster.asl M src/soc/intel/skylake/acpi/systemagent.asl 14 files changed, 38 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/75729/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4 Gerrit-Change-Number: 75729 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: soc/mediatek/common: Disable DRAM scramble by default
by Yidi Lin (Code Review) 08 Jun '23

08 Jun '23

Attention is currently required from: Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75562?usp=email ) Change subject: soc/mediatek/common: Disable DRAM scramble by default ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75562/comment/d5432678_fc7b0be0 : PS3, Line 16: > add BRANCH=corsola This feature only implements on geralt and the corsola branch does not have this config. -- To view, visit https://review.coreboot.org/c/coreboot/+/75562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I109634d811a928e3e6f7f56e706a5b61a52a21ab Gerrit-Change-Number: 75562 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 08 Jun 2023 13:31:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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