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Change subject: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable devicetree option
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/skylake/chip.h:
https://review.coreboot.org/c/coreboot/+/75871/comment/3cdadb27_d9803bed :
PS4, Line 15: #include <stdbool.h>
: #include <stdint.h>
> could be cleaned up in a separate step.
Oh, nevermind the order, I thought stdint was new because it's highlighted.
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Change subject: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable devicetree option
......................................................................
Patch Set 4:
(2 comments)
Patchset:
PS3:
> It would allow to use more natural language. To me, neither `_enabled = 1` nor […]
I like the idea, though it feels like overengineering. I wouldn't like to invent a new keyword just because it sounds more natural. This would apply to many things. I guess it would be even more confusing.. When should people use true/false and when enable/disable?
Using true/false this way is totally fine for me
```
register s0ix = true
```
File src/soc/intel/skylake/chip.h:
https://review.coreboot.org/c/coreboot/+/75871/comment/1de03e70_7a6b2b38 :
PS4, Line 15: #include <stdbool.h>
: #include <stdint.h>
> Shouldn't we leave this decision to the author? […]
could be cleaned up in a separate step.
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Change subject: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable devicetree option
......................................................................
Patch Set 4:
(2 comments)
Patchset:
PS3:
> I agree with Felix and don't see a reason for a enum tbh
It would allow to use more natural language. To me, neither `_enabled = 1` nor
`_enabled = true` feels right.
File src/soc/intel/skylake/chip.h:
https://review.coreboot.org/c/coreboot/+/75871/comment/f47aea39_0b43d787 :
PS4, Line 15: #include <stdbool.h>
: #include <stdint.h>
> #include <types. […]
Shouldn't we leave this decision to the author?
Btw. the list seems sorted alphabetically, `std` would come after `soc`.
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Change subject: acpi: Add SPCR table
......................................................................
Patch Set 5: Code-Review+1
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Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/bytedance/bd_egs/bootblock.c:
https://review.coreboot.org/c/coreboot/+/75722/comment/efabbee2_34822b9a :
PS6, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
> Yiwei, I would think unifying all license declaration to GOL-2.0-or-later is fine.
If the file is based on another we can't extend the license without
permission by the copyright owner. If we can change -later to -only,
I don't know. Overall, it seems not worth the time to change anything
as long as it's GPL v2 compatible.
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Change subject: soc/intel/cmd/blk/cse: Implement APIs to access FW versions in CMOS
......................................................................
Patch Set 42:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/cse_lite_cmos.h:
https://review.coreboot.org/c/coreboot/+/74995/comment/892ca559_3037278d :
PS41, Line 19:
> > Yes, it is true that the CMOS APIs are local to CSE Lite and do not need to be exposed outside of […]
Acknowledged
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Hello Kapil Porwal, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Verified+1 by build bot (Jenkins)
Change subject: soc/intel/cmd/blk/cse: Store fw versions in CMOS memory for cold boot
......................................................................
soc/intel/cmd/blk/cse: Store fw versions in CMOS memory for cold boot
During a cold reboot, the CBMEM memory resets and loses the stored
firmware versions. This causes the firmware versions to be fetched again
from the CSE, which increases the boot time by about 200 ms. This patch
stores a backup of the firmware version in CMOS and updates the CBMEM
memory during a cold reboot.
BUG=b:280722061
Test=Verified the changes on nissa board.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: Ibc5a027aa2bb7217e5032f56fece0846783557a5
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 55 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/75755/13
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Hello Kapil Porwal, Sridhar Siricilla, Subrata Banik, build bot (Jenkins),
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Verified+1 by build bot (Jenkins)
Change subject: soc/intel/cmd/blk/cse: Implement APIs to access FW versions in CMOS
......................................................................
soc/intel/cmd/blk/cse: Implement APIs to access FW versions in CMOS
This patch implements APIs to access the FW versions in CMOS. The get
API allows users to retrieve the current version from CMOS memory.
The set API allows users to set the version in CMOS memory.
BUG=b:280722061
TEST=APIs verified on nivviks and marasov board.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: Idd0ee19575683691c0a82a291e1fd3b2ffb11786
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
A src/soc/intel/common/block/cse/cse_lite_cmos.c
A src/soc/intel/common/block/cse/cse_lite_cmos.h
4 files changed, 214 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/74995/42
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