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Change subject: mb/google/rex/var/screebo: rp0/rp2 change to rp1/rp3
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75832/comment/6bd70fa7_0bc6e09d :
PS6, Line 7: rp0/rp2 change to rp1/rp3
Please use imperative mood: Change rp0/rp2 to rp1/rp2.
https://review.coreboot.org/c/coreboot/+/75832/comment/04cda2e0_8e6c3c71 :
PS6, Line 9: rp0/rp2 change to rp1/rp3 for TCP1 and TCP3
Why? What is the source for your change?
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Change subject: mb/google/rex/var/screebo: rp0/rp2 change to rp1/rp3
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS2:
> Can you please rewording the comment.
Acknowledged
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Change subject: ec/google/chromeec: Use mux_conn to get the right USB port
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75824/comment/04836b96_7718bd44 :
PS2, Line 9: get_usb_port_references
Can't we use PLD to fix this issue?
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Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs
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Patch Set 7:
(1 comment)
File src/mainboard/bytedance/bd_egs/gpio.h:
https://review.coreboot.org/c/coreboot/+/75722/comment/33fcd43e_c1096fcd :
PS7, Line 6: include <soc/gpio.h>
"include <gpio.h>" instead
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Change subject: acpi: Add SPCR table
......................................................................
Patch Set 5: Code-Review+2
(2 comments)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/75685/comment/0ebb4ab6_5d36cbf2 :
PS3, Line 1870: /* TODO: provide callback for IRQ on non standard ports*/
> > Would it be bad not to use an IRQ at all? […]
that should work for the earlycon, it looks like Linux doesn't use interrupts for the early console
File src/include/acpi/acpi.h:
https://review.coreboot.org/c/coreboot/+/75685/comment/097c0dbd_274ba245 :
PS5, Line 1336: #define RISCV_PLIC_COMPATIBLE_INTERRUPT (1 << 4)
minor nit: I won't hold up the patch, but would be nice to align the right sides
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Change subject: soc/intel/xeon_sp: add Kconfig file for SPR-SP
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Patch Set 8:
(2 comments)
File src/soc/intel/xeon_sp/spr/Kconfig:
https://review.coreboot.org/c/coreboot/+/72439/comment/e6114ce1_2c82099b :
PS8, Line 128: MAX_IMC
maybe I'm wrong, but isn't this defined here intel/fsp/fsp2_0/sapphirerapids_sp/IioUniversalDataHob.h ?
https://review.coreboot.org/c/coreboot/+/72439/comment/bc91ceac_e5f1641a :
PS8, Line 132: MAX_MC_CHN
this is not used
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Change subject: mb/google/kahlee: Enable secure OS
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75874/comment/dc64efa6_3f78ba72 :
PS5, Line 10: risks
Just out of curiosity: The help text of the Kconfig doesn't mention
any risks. Is this just to reduce attack surface or was there anything
specific?
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