coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/brya/var/vell: update FW_config to sync config.star
by Shon Wang (Code Review) 19 Jun '23

19 Jun '23

Shon Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75913?usp=email ) Change subject: mb/google/brya/var/vell: update FW_config to sync config.star ...................................................................... mb/google/brya/var/vell: update FW_config to sync config.star We have found inconsistencies in turn of FW_CONFIG settings/definitions, so sync setting to vell config.star BUG=b:282189358 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I676b719ecc711a6f59e76465a3566bf63924d90f Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/vell/overridetree.cb 1 file changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/75913/1 diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 1100628..c8e6799 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -1,25 +1,41 @@ fw_config - field DB_SD 0 1 + field DB_CELLULAR 0 0 + option DB_CELLULAR_ABSENT 0 + option DB_CELLULAR_PCIE 1 + end + field KB_COLOR 1 1 + option KB_COLOR_WHITE 0 + option KB_COLOR_BLUE 1 + end + field NAND 2 2 + option NAND_MICRON 0 + option NAND_KIOXIA 1 + end + field DB_SD 3 4 option SD_ABSENT 0 option SD_GL9750 1 end - field KB_BL 2 2 + field KB_BL 5 5 option KB_BL_ABSENT 0 option KB_BL_PRESENT 1 end - field AUDIO 3 5 + field AUDIO 6 8 option AUDIO_UNKNOWN 0 option MAX98360_ALC5682I_I2S 1 option MAX98360_ALC5682IVS_I2S 2 end - field DB_LTE 6 7 + field DB_LTE 9 10 option LTE_ABSENT 0 option LTE_USB 1 end - field EPS 10 10 + field EPS 11 11 option PRIVACY_SCREEN_ABSENT 0 option PRIVACY_SCREEN 1 end + field WIFI_SAR_ID 30 31 + option WIFI_SAR_ID_0 0 + option WIFI_SAR_ID_1 1 + end end chip soc/intel/alderlake # Intel Common SoC Config -- To view, visit https://review.coreboot.org/c/coreboot/+/75913?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I676b719ecc711a6f59e76465a3566bf63924d90f Gerrit-Change-Number: 75913 Gerrit-PatchSet: 1 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/hades: Update typeC usb PLD
by Eric Lai (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli. Hello Kapil Porwal, Subrata Banik, Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75912?usp=email to look at the new patch set (#2). Change subject: mb/google/hades: Update typeC usb PLD ...................................................................... mb/google/hades: Update typeC usb PLD get_usb_port_references refer the PLD group. If the port assign cross ports like mux[0] use USB3 and mux[1] use USB1, then we need set USB3 to group 1. BUG=b:286328285 TEST=check ACPI can have right USB port in EC CON. Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I97517ecd4f8615af749fb6d007ded8e171796f7c --- M src/mainboard/google/brya/variants/hades/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/75912/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75912?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97517ecd4f8615af749fb6d007ded8e171796f7c Gerrit-Change-Number: 75912 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/google/hades: Update typeC usb PLD
by Eric Lai (Code Review) 19 Jun '23

19 Jun '23

Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75912?usp=email ) Change subject: mb/google/hades: Update typeC usb PLD ...................................................................... mb/google/hades: Update typeC usb PLD get_usb_port_references refer the PLD group. If the port assign cross ports like mux[0] use USB3 and mux[1] use USB1, then we need set USB3 to group 1. BUG=b:286328285 TEST=check ACPI can have right USB port in EC CON. Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I97517ecd4f8615af749fb6d007ded8e171796f7c --- M src/mainboard/google/brya/variants/hades/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/75912/1 diff --git a/src/mainboard/google/brya/variants/hades/overridetree.cb b/src/mainboard/google/brya/variants/hades/overridetree.cb index 1412a1f..8ecff50 100644 --- a/src/mainboard/google/brya/variants/hades/overridetree.cb +++ b/src/mainboard/google/brya/variants/hades/overridetree.cb @@ -289,14 +289,14 @@ register "desc" = ""USB3 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port3 on end end end @@ -309,14 +309,14 @@ register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/75912?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97517ecd4f8615af749fb6d007ded8e171796f7c Gerrit-Change-Number: 75912 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: ec/google/chromeec: Use mux_conn to get the right USB port
by Eric Lai (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Kapil Porwal, Tarun Tuli, Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75824?usp=email ) Change subject: ec/google/chromeec: Use mux_conn to get the right USB port ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75824/comment/07db438a_dce511d6 : PS2, Line 9: get_usb_port_references > My issue is on hades , and already group type A to 3 I think I got why the issue always hit now. We always start the PLD group in order, but we won't make it to match the mux_conn, if we want to fix it, we should use mux_conn to set the PLD.... -- To view, visit https://review.coreboot.org/c/coreboot/+/75824?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I058c6cc0fea6758bfaafdd163b5da2c7f75daf8a Gerrit-Change-Number: 75824 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Mon, 19 Jun 2023 05:34:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
by Eric Lai (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Arthur Heymans, Felix Singer, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun Tuli. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75756?usp=email ) Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config ...................................................................... Patch Set 14: (1 comment) File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/75756/comment/4efe5743_f19e7571 : PS9, Line 226: /* skip old type for save static memory : "Other", : "Unknown", : "DRAM", : "EDRAM", : "VRAM", : "SRAM", : "RAM", : "ROM", : "Flash", : "EEPROM", : "FEPROM", : "EPROM", : "CDRAM", : "3DRAM", : "SDRAM", : "SGRAM", : "RDRAM", : "DDR", : "DDR2", : "DDR2 FB-DIMM", : "Reserved", : "Reserved", : "Reserved", : "DDR3", : "FBD2", : */ > I think we should have all the known types included. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5ca1f4a59598531a6cba500672c2717f2a7b00 Gerrit-Change-Number: 75756 Gerrit-PatchSet: 14 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 19 Jun 2023 05:22:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: ec/google/chromeec: Use mux_conn to get the right USB port
by Eric Lai (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Kapil Porwal, Tarun Tuli, Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75824?usp=email ) Change subject: ec/google/chromeec: Use mux_conn to get the right USB port ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75824/comment/5e0e2809_dc013e5f : PS2, Line 9: get_usb_port_references > check the below code in `get_usb_port_references` - […] My issue is on hades , and already group type A to 3 -- To view, visit https://review.coreboot.org/c/coreboot/+/75824?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I058c6cc0fea6758bfaafdd163b5da2c7f75daf8a Gerrit-Change-Number: 75824 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Mon, 19 Jun 2023 05:08:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
by Kapil Porwal (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Arthur Heymans, Eric Lai, Felix Singer, Paul Menzel, Subrata Banik, Tarun Tuli. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75756?usp=email ) Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config ...................................................................... Patch Set 13: (1 comment) File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/75756/comment/70e94615_30c581af : PS9, Line 226: /* skip old type for save static memory : "Other", : "Unknown", : "DRAM", : "EDRAM", : "VRAM", : "SRAM", : "RAM", : "ROM", : "Flash", : "EEPROM", : "FEPROM", : "EPROM", : "CDRAM", : "3DRAM", : "SDRAM", : "SGRAM", : "RDRAM", : "DDR", : "DDR2", : "DDR2 FB-DIMM", : "Reserved", : "Reserved", : "Reserved", : "DDR3", : "FBD2", : */ > Anyone else have idea here? I think we should have all the known types included. Even this `"below MEMORY_TYPE_DDR4 or exceed MEMORY_TYPE_HBM3"` string is occupying some static area. -- To view, visit https://review.coreboot.org/c/coreboot/+/75756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5ca1f4a59598531a6cba500672c2717f2a7b00 Gerrit-Change-Number: 75756 Gerrit-PatchSet: 13 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 19 Jun 2023 04:48:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Print crashlog size info in hex
by Kapil Porwal (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Pratikkumar V Prajapati, Subrata Banik, Tarun Tuli. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75910?usp=email ) Change subject: soc/intel/common: Print crashlog size info in hex ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75910?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb5498e702497bfbc2b4d5396d5b760a0010f5de Gerrit-Change-Number: 75910 Gerrit-PatchSet: 4 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Mon, 19 Jun 2023 04:22:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/meteorlake: Add support for crashlog
by Kapil Porwal (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Eric Lai, Kane Chen, Paul Menzel, Pratikkumar V Prajapati, Subrata Banik, Tarun Tuli. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74769?usp=email ) Change subject: soc/intel/meteorlake: Add support for crashlog ...................................................................... Patch Set 24: (1 comment) File src/soc/intel/meteorlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/74769/comment/43284ca8_4124b1e0 : PS24, Line 63: pcireg = pci_read_config16(sram_dev, PCI_COMMAND); : pcireg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY); : pci_write_config16(sram_dev, PCI_COMMAND, pcireg); can we use `pci_update_config16`? -- To view, visit https://review.coreboot.org/c/coreboot/+/74769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Gerrit-Change-Number: 74769 Gerrit-PatchSet: 24 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Mon, 19 Jun 2023 04:21:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: ec/google/chromeec: Use mux_conn to get the right USB port
by Kapil Porwal (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Eric Lai, Tarun Tuli, Tim Wawrzynczak. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75824?usp=email ) Change subject: ec/google/chromeec: Use mux_conn to get the right USB port ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75824/comment/90677a31_831b894a : PS2, Line 9: get_usb_port_references > Search through the devicetree for matching USB Type-C ports, will always report the port by device t […] check the below code in `get_usb_port_references` - ``` int group_token; if (config->use_custom_pld) group_token = config->custom_pld.group.token; else group_token = config->group.token; if (group_token != (port_number + 1)) continue; ``` I think current PLD for Type-A port `ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))` is causing this issue. Could you please try https://review.coreboot.org/c/coreboot/+/75911 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/75824?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I058c6cc0fea6758bfaafdd163b5da2c7f75daf8a Gerrit-Change-Number: 75824 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Mon, 19 Jun 2023 04:16:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2023