coreboot-gerrit June 2023

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[S] Change in coreboot[master]: soc/intel/apollolake: Fix FSP SATA speed limit configuraion
by Jakub Czapiga (Code Review) 19 Jun '23

19 Jun '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75820?usp=email ) Change subject: soc/intel/apollolake: Fix FSP SATA speed limit configuraion ...................................................................... soc/intel/apollolake: Fix FSP SATA speed limit configuraion With commit f165bbdcf043 ("soc/intel/apollolake: Make SATA speed limit configurable") came the expansion to adjust the SATA speed. Unfortunately, APL FSP-S sets only the default value, so Gen 3, and ignores the passing parameter value. Since the corresponding register entry can only be changed once, the setting must be made on coreboot side before FSP-S is called. This patch fixes the SATA speed configuration for Apollo Lake CPUs. Link to Intel Pentium and Celeron N- and J- series datasheet volume 2: https://web.archive.org/web/20230614130311/https://www.intel.com/content/ww… BUG=none TEST=Boot into Linux and check SATA configuration via dmesg ahci 0000:00:12.0: AHCI 0001.0301 32 slots 1 ports 3 Gbps 0x1 impl SATA mode ata1: SATA max UDMA/133 abar m2048@0x9872a000 port 0x9872a100 irq 126 ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300) Change-Id: I6f55f40941fa618e7de13a5cefe9e17ae34c5c99 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75820 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/apollolake/Makefile.inc A src/soc/intel/apollolake/ahci.c M src/soc/intel/apollolake/chip.c A src/soc/intel/apollolake/include/soc/ahci.h 4 files changed, 48 insertions(+), 1 deletion(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 107a913..82937bc 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -46,6 +46,7 @@ smm-y += xhci.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-y += ahci.c ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += cse.c diff --git a/src/soc/intel/apollolake/ahci.c b/src/soc/intel/apollolake/ahci.c new file mode 100644 index 0000000..39121d7 --- /dev/null +++ b/src/soc/intel/apollolake/ahci.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/pci_ops.h> +#include <soc/ahci.h> +#include <soc/pci_devs.h> +#include <soc/soc_chip.h> +#include <types.h> + +void ahci_set_speed(enum sata_speed_limit speed) +{ + if (speed == SATA_DEFAULT) + return; + + /* Setup temporary base address for BAR5. */ + pci_write_config32(PCH_DEV_SATA, PCI_BASE_ADDRESS_5, AHCI_TMP_BASE_ADDR); + /* Enable memory access for pci_dev. */ + pci_or_config16(PCH_DEV_SATA, PCI_COMMAND, PCI_COMMAND_MEMORY); + + printk(BIOS_DEBUG, "AHCI: Set SATA speed to Gen %d\n", speed); + clrsetbits32((void *)(AHCI_TMP_BASE_ADDR + AHCI_CAP), AHCI_CAP_ISS_MASK, + AHCI_SPEED(speed)); + + /* Disable memory access for pci_dev. */ + pci_and_config16(PCH_DEV_SATA, PCI_COMMAND, ~PCI_COMMAND_MEMORY); + /* Clear temporary base address for BAR5. */ + pci_write_config32(PCH_DEV_SATA, PCI_BASE_ADDRESS_5, 0); +} diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 04aa2eb..9ec52b1 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -24,6 +24,7 @@ #include <intelblocks/pmclib.h> #include <intelblocks/systemagent.h> #include <option.h> +#include <soc/ahci.h> #include <soc/cpu.h> #include <soc/heci.h> #include <soc/intel/common/vbt.h> @@ -736,7 +737,7 @@ /* SATA config */ if (is_devfn_enabled(PCH_DEVFN_SATA)) { silconfig->SataSalpSupport = !(cfg->DisableSataSalpSupport); - silconfig->SpeedLimit = cfg->sata_speed; + ahci_set_speed(cfg->sata_speed); memcpy(silconfig->SataPortsEnable, cfg->sata_ports_enable, sizeof(silconfig->SataPortsEnable)); memcpy(silconfig->SataPortsSolidStateDrive, cfg->sata_ports_ssd, diff --git a/src/soc/intel/apollolake/include/soc/ahci.h b/src/soc/intel/apollolake/include/soc/ahci.h new file mode 100644 index 0000000..d129979 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/ahci.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_APOLLOLAKE_AHCI_H_ +#define _SOC_APOLLOLAKE_AHCI_H_ + +#include <soc/soc_chip.h> + +#define AHCI_TMP_BASE_ADDR 0x9872c000 + +#define AHCI_CAP 0x0 +#define AHCI_CAP_ISS_MASK 0x00f00000 +#define AHCI_SPEED(speed) (speed << 20) + +/* Set SATA controller speed. */ +void ahci_set_speed(enum sata_speed_limit speed); + +#endif /* _SOC_APOLLOLAKE_AHCI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/75820?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f55f40941fa618e7de13a5cefe9e17ae34c5c99 Gerrit-Change-Number: 75820 Gerrit-PatchSet: 10 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/google/rex/var/screebo: Remove rp2 and add rp1/rp3
by Kun Liu (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Eric Lai, Kane Chen, Kapil Porwal, Paul Menzel, Rui Zhou, Subrata Banik, Tarun Tuli. Kun Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75832?usp=email ) Change subject: mb/google/rex/var/screebo: Remove rp2 and add rp1/rp3 ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75832/comment/79ca996f_5d76763a : PS6, Line 9: rp0/rp2 change to rp1/rp3 for TCP1 and TCP3 > screebo use tcp1 and tpc3, please see https://docs.google. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1013d26c705f2a3f9378d944bd863d94f319d36c Gerrit-Change-Number: 75832 Gerrit-PatchSet: 8 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Simon Zhou <zhouguohui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 19 Jun 2023 08:13:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex/var/screebo: Remove rp2 and add rp1/rp3
by Simon Zhou (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Eric Lai, Kane Chen, Kapil Porwal, Kun Liu, Paul Menzel, Rui Zhou, Subrata Banik, Tarun Tuli. Simon Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75832?usp=email ) Change subject: mb/google/rex/var/screebo: Remove rp2 and add rp1/rp3 ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1013d26c705f2a3f9378d944bd863d94f319d36c Gerrit-Change-Number: 75832 Gerrit-PatchSet: 8 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Simon Zhou <zhouguohui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 19 Jun 2023 08:09:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex/var/screebo: Remove rp2 and add rp1/rp3
by Kun Liu (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Eric Lai, Kapil Porwal, Paul Menzel, Rui Zhou, Simon Zhou, Subrata Banik, Tarun Tuli. Kun Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75832?usp=email ) Change subject: mb/google/rex/var/screebo: Remove rp2 and add rp1/rp3 ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: Keep rp0, otherwise there will be remap problem. https://partnerissuetracker.corp.google.com/issues/283053968 #75 -- To view, visit https://review.coreboot.org/c/coreboot/+/75832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1013d26c705f2a3f9378d944bd863d94f319d36c Gerrit-Change-Number: 75832 Gerrit-PatchSet: 8 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Simon Zhou <zhouguohui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Simon Zhou <zhouguohui(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 19 Jun 2023 08:08:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex/var/screebo: Remove rp2 and add rp1/rp3
by Kun Liu (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Eric Lai, Kapil Porwal, Kun Liu, Paul Menzel, Rui Zhou, Simon Zhou, Subrata Banik, Tarun Tuli. Kun Liu has uploaded a new patch set (#8) to the change originally created by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/75832?usp=email ) The following approvals got outdated and were removed: Code-Review+1 by Simon Zhou, Code-Review+2 by Kapil Porwal, Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: mb/google/rex/var/screebo: Remove rp2 and add rp1/rp3 ...................................................................... mb/google/rex/var/screebo: Remove rp2 and add rp1/rp3 Remove rp2 and add rp1/rp3 for screebo BUG=b:286187816 BRANCH=none TEST=emerge-rex coreboot and verify TBT works. Change-Id: I1013d26c705f2a3f9378d944bd863d94f319d36c Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/rex/variants/screebo/overridetree.cb 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/75832/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/75832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1013d26c705f2a3f9378d944bd863d94f319d36c Gerrit-Change-Number: 75832 Gerrit-PatchSet: 8 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Simon Zhou <zhouguohui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Simon Zhou <zhouguohui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/nissa/var/joxer: Update Joxer GPIO
by Terry Chen (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Derek Huang, Shou-Chieh Hsu, Tarun Tuli. Terry Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75914?usp=email ) Change subject: mb/google/nissa/var/joxer: Update Joxer GPIO ...................................................................... Patch Set 4: (2 comments) File src/mainboard/google/brya/variants/joxer/gpio.c: https://review.coreboot.org/c/coreboot/+/75914/comment/1c0811ac_fead28c6 : PS3, Line 46: PAD_NC > PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), Done https://review.coreboot.org/c/coreboot/+/75914/comment/2dda6f2a_3bac9a19 : PS3, Line 48: PAD_NC(GPP_H13, NONE), > same as above Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75914?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a55058b453771d264700a1364ef538f831148e4 Gerrit-Change-Number: 75914 Gerrit-PatchSet: 4 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Mon, 19 Jun 2023 07:47:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/hades: Update typeC usb PLD
by Eric Lai (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli. Hello Kapil Porwal, Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75912?usp=email to look at the new patch set (#5). Change subject: mb/google/hades: Update typeC usb PLD ...................................................................... mb/google/hades: Update typeC usb PLD get_usb_port_references refer the PLD group. If the port assign cross ports like mux[0] use USB3 and mux[1] use USB1, then we need set USB3 to group 1. Update the PLD panel to back as well. BUG=b:286328285 TEST=check ACPI can have right USB port in EC CON. Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I97517ecd4f8615af749fb6d007ded8e171796f7c --- M src/mainboard/google/brya/variants/hades/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/75912/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/75912?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97517ecd4f8615af749fb6d007ded8e171796f7c Gerrit-Change-Number: 75912 Gerrit-PatchSet: 5 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/nissa/var/joxer: Update Joxer GPIO
by Derek Huang (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Shou-Chieh Hsu, Tarun Tuli, Terry Chen. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75914?usp=email ) Change subject: mb/google/nissa/var/joxer: Update Joxer GPIO ...................................................................... Patch Set 3: (2 comments) File src/mainboard/google/brya/variants/joxer/gpio.c: https://review.coreboot.org/c/coreboot/+/75914/comment/e9583d30_5c9f8384 : PS3, Line 46: PAD_NC PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), https://review.coreboot.org/c/coreboot/+/75914/comment/608c24e4_967a13e8 : PS3, Line 48: PAD_NC(GPP_H13, NONE), same as above -- To view, visit https://review.coreboot.org/c/coreboot/+/75914?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a55058b453771d264700a1364ef538f831148e4 Gerrit-Change-Number: 75914 Gerrit-PatchSet: 3 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Mon, 19 Jun 2023 07:34:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/hades: Update typeC usb PLD
by Eric Lai (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75912?usp=email ) Change subject: mb/google/hades: Update typeC usb PLD ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: After change the PLD panel, kernel gets right too. [ 4.984623] typec port0: bound usb3-port1 (ops 0xffffffffa9200b18) [ 4.984647] typec port0: bound usb2-port3 (ops 0xffffffffa9200b18) [ 4.999192] typec port1: bound usb3-port3 (ops 0xffffffffa9200b18) [ 4.999560] typec port1: bound usb2-port1 (ops 0xffffffffa9200b18) -- To view, visit https://review.coreboot.org/c/coreboot/+/75912?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97517ecd4f8615af749fb6d007ded8e171796f7c Gerrit-Change-Number: 75912 Gerrit-PatchSet: 4 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 19 Jun 2023 07:20:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/dedede/var/dibbi: Update power limits
by ChiaLing (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Reka Norman, Sumeet R Pawnikar, Zhuohao Lee. ChiaLing has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75681?usp=email ) Change subject: mb/google/dedede/var/dibbi: Update power limits ...................................................................... Patch Set 10: (2 comments) File src/mainboard/google/dedede/variants/dibbi/ramstage.c: https://review.coreboot.org/c/coreboot/+/75681/comment/a23afea6_285b0d3e : PS9, Line 16: 6000 > In devicetree this is set to 3000. […] Removed. https://review.coreboot.org/c/coreboot/+/75681/comment/25e719fd_10aa6f4d : PS9, Line 66: variant_update_cpu_power_limits(pwr_limits, total_entries); > Did you test this? It's not working for me because the common code uses `DEV_PTR(dptf_policy)` which […] Update new code to review. -- To view, visit https://review.coreboot.org/c/coreboot/+/75681?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6 Gerrit-Change-Number: 75681 Gerrit-PatchSet: 10 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chia-Ling Hou <chia-ling.hou(a)intel.corp-partner.google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Mon, 19 Jun 2023 07:09:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

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