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Change subject: mb/google/dedede: Support variant specific power limits
......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/google/dedede/variants/baseboard/ramstage.c:
https://review.coreboot.org/c/coreboot/+/75680/comment/84c22634_75046e8d :
PS8, Line 93: sys_limits[dedede_idx].psys_pl2_power
> Could you please use 97% of the BJ power as Ben suggested. […]
Done
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Change subject: mb/google/dedede/var/dibbi: Update power limits
......................................................................
mb/google/dedede/var/dibbi: Update power limits
Add ramstage.c in Makefile.inc and update Dibbi power limit in ramstage.
BUG=b:281479111
TEST=emerge-dedede coreboot and check psys and PLx value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com>
Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6
---
M src/mainboard/google/dedede/variants/dibbi/Makefile.inc
A src/mainboard/google/dedede/variants/dibbi/ramstage.c
2 files changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/75681/10
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Change subject: mb/google/dedede: Support variant specific power limits
......................................................................
mb/google/dedede: Support variant specific power limits
With newer dedede design, it's required to config corresponding
psyspmax, psyspl1, psyspl2, pl1 and pl2 by different kinds of
adapter.
BUG=b:281479111
TEST=emerge-dedede coreboot and check correct value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com>
Change-Id: I583c930379233322c41027805369f81d02000ee7
---
M src/mainboard/google/dedede/variants/baseboard/Makefile.inc
M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/dedede/variants/baseboard/ramstage.c
3 files changed, 104 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/75680/9
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Change subject: mb/inventec: Add Intel SPR server board Inventec Transformers
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS5:
> Done
Hi Felix,
I'm working on making this into a variant of Archer City now. You're correct that a substantial amount of code is shared with the Archer City CRB, however there are a couple of additions in GPIO assignment, IPMI commands, and SMBIOS info.
Is there a particular example of a variant you think might be useful here? One important difference is that with server products we do not expect a single hardware configuration; we expect differences in things like max sockets, PCIe bifurcation/lane config, BMC commands (due to different BMC firmwares out there and OEM-specific commands), and GPIO assignments.
So the baseboard Makefile.inc and Kconfig might not be as pretty in our case, but it may still be a good tradeoff to reduce duplicated code.
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Change subject: soc/intel/meteorlake: Set Energy Perf Bias appropriate default value.
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75907/comment/ff2ad5d7_de670822 :
PS1, Line 7: soc/intel/meteorlake: Set Energy Perf Bias appropriate default value.
> Maybe: Default to Balance_Powersave policy
>
> (How is it spelled in the datasheet?)
Set EPB policy to Balance_Powersave
https://review.coreboot.org/c/coreboot/+/75907/comment/6927b02d_e7097c90 :
PS1, Line 10: best PnP user experience
> How is that measured? Plug and Play? Doesn’t it depend on the board?
Power and Performance
File src/include/cpu/x86/msr.h:
https://review.coreboot.org/c/coreboot/+/75907/comment/c647a748_7e74821c :
PS1, Line 54:
tab?
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