coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for ModPhyVoltageBump
by Jakub Czapiga (Code Review) 19 Jun '23

19 Jun '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75856?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/apollolake: Switch to snake case for ModPhyVoltageBump ...................................................................... soc/intel/apollolake: Switch to snake case for ModPhyVoltageBump For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyVoltageBump'. Change-Id: Ic1e743e23bdfc45588411c584eecb839cc552faf Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75856 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index a29ba3b..956a55b 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -617,7 +617,7 @@ /* * Options to bump USB3 LDO voltage with 40mv. */ - silconfig->ModPhyVoltageBump = cfg->ModPhyVoltageBump; + silconfig->ModPhyVoltageBump = cfg->mod_phy_voltage_bump; /* * Options to adjust PMIC Vdd2 voltage. diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 26e4478..5a3aa88 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -196,7 +196,7 @@ * LDO voltage. Set TRUE to increase LDO voltage with 40mV. * 0:FALSE (default), 1:True. */ - uint8_t ModPhyVoltageBump; + uint8_t mod_phy_voltage_bump; /* Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting * the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage -- To view, visit https://review.coreboot.org/c/coreboot/+/75856?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e743e23bdfc45588411c584eecb839cc552faf Gerrit-Change-Number: 75856 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for ModPhyIfValue
by Jakub Czapiga (Code Review) 19 Jun '23

19 Jun '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75855?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/apollolake: Switch to snake case for ModPhyIfValue ...................................................................... soc/intel/apollolake: Switch to snake case for ModPhyIfValue For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyIfValue'. Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75855 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/starlabs/lite/variants/glk/devicetree.cb M src/mainboard/starlabs/lite/variants/glkr/devicetree.cb M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 5 files changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index fdfcd61..c6bfe54 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -290,5 +290,5 @@ # FSP UPD to modify the Integrated Filter (IF) value # Set it to default value: 0x12 - register "ModPhyIfValue" = "0x12" + register "mod_phy_if_value" = "0x12" end diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb index abfbc0a..2f58a7b 100644 --- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb @@ -26,7 +26,7 @@ register "pnp_settings" = "PNP_PERF_POWER" - register "ModPhyIfValue" = "0x12" + register "mod_phy_if_value" = "0x12" register "prt0_gpio" = "GPIO_PRT0_UDEF" diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index 3102b1f..fe32143c5d 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -26,7 +26,7 @@ register "pnp_settings" = "PNP_PERF_POWER" - register "ModPhyIfValue" = "0x12" + register "mod_phy_if_value" = "0x12" register "prt0_gpio" = "GPIO_PRT0_UDEF" diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index e3bfa1e..a29ba3b 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -612,7 +612,7 @@ /* * Options to change USB3 ModPhy setting for Integrated Filter value. */ - silconfig->ModPhyIfValue = cfg->ModPhyIfValue; + silconfig->ModPhyIfValue = cfg->mod_phy_if_value; /* * Options to bump USB3 LDO voltage with 40mv. diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index c1bc020..26e4478 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -190,7 +190,7 @@ * value. Default is 0 to not changing default IF value (0x12). Set * value with the range from 0x01 to 0xff to change IF value. */ - uint8_t ModPhyIfValue; + uint8_t mod_phy_if_value; /* Options to bump USB3 LDO voltage. Default is FALSE to not increasing * LDO voltage. Set TRUE to increase LDO voltage with 40mV. -- To view, visit https://review.coreboot.org/c/coreboot/+/75855?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d Gerrit-Change-Number: 75855 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for DisableComplianceMode
by Jakub Czapiga (Code Review) 19 Jun '23

19 Jun '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75854?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/apollolake: Switch to snake case for DisableComplianceMode ...................................................................... soc/intel/apollolake: Switch to snake case for DisableComplianceMode For a unification of the naming convension, change from pascal case to snake case style for parameter 'DisableComplianceMode'. Change-Id: I9d5605134a753f161a66857c7f78844ae7490cd6 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75854 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/google/octopus/variants/bloog/overridetree.cb M src/mainboard/google/octopus/variants/bobba/overridetree.cb M src/mainboard/google/octopus/variants/casta/overridetree.cb M src/mainboard/google/octopus/variants/dood/overridetree.cb M src/mainboard/google/octopus/variants/fleex/overridetree.cb M src/mainboard/google/octopus/variants/foob/overridetree.cb M src/mainboard/google/octopus/variants/garg/overridetree.cb M src/mainboard/google/octopus/variants/lick/overridetree.cb M src/mainboard/google/octopus/variants/meep/overridetree.cb M src/mainboard/google/octopus/variants/phaser/overridetree.cb M src/mainboard/starlabs/lite/variants/glk/devicetree.cb M src/mainboard/starlabs/lite/variants/glkr/devicetree.cb M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 14 files changed, 14 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/google/octopus/variants/bloog/overridetree.cb b/src/mainboard/google/octopus/variants/bloog/overridetree.cb index 83880ec..b4388c1 100644 --- a/src/mainboard/google/octopus/variants/bloog/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bloog/overridetree.cb @@ -168,5 +168,5 @@ end # Disable compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" end diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 8a48d22..31c1463 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -227,6 +227,6 @@ end # Disable compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/casta/overridetree.cb b/src/mainboard/google/octopus/variants/casta/overridetree.cb index dce4d00..c7540c8 100644 --- a/src/mainboard/google/octopus/variants/casta/overridetree.cb +++ b/src/mainboard/google/octopus/variants/casta/overridetree.cb @@ -150,5 +150,5 @@ end # Disable compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" end diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index de923c4..9b4126d 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -162,6 +162,6 @@ end # Disable compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 9a4cdee..b8444e5 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -85,7 +85,7 @@ }" # Disable compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" register "disable_xhci_lfps_pm" = "0" device domain 0 on diff --git a/src/mainboard/google/octopus/variants/foob/overridetree.cb b/src/mainboard/google/octopus/variants/foob/overridetree.cb index c47b0de..274aead 100644 --- a/src/mainboard/google/octopus/variants/foob/overridetree.cb +++ b/src/mainboard/google/octopus/variants/foob/overridetree.cb @@ -163,5 +163,5 @@ end # Disable xHCI compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" end diff --git a/src/mainboard/google/octopus/variants/garg/overridetree.cb b/src/mainboard/google/octopus/variants/garg/overridetree.cb index 86b4342..459e5b3 100644 --- a/src/mainboard/google/octopus/variants/garg/overridetree.cb +++ b/src/mainboard/google/octopus/variants/garg/overridetree.cb @@ -204,6 +204,6 @@ end # Disable compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" register "disable_xhci_lfps_pm" = "0" end diff --git a/src/mainboard/google/octopus/variants/lick/overridetree.cb b/src/mainboard/google/octopus/variants/lick/overridetree.cb index b74417b..551a2ba 100644 --- a/src/mainboard/google/octopus/variants/lick/overridetree.cb +++ b/src/mainboard/google/octopus/variants/lick/overridetree.cb @@ -116,5 +116,5 @@ # Disable compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" end diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb index 6623fa0..727b468 100644 --- a/src/mainboard/google/octopus/variants/meep/overridetree.cb +++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb @@ -248,5 +248,5 @@ end # Disable compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" end diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb index 748481d..472676f 100644 --- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb +++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb @@ -202,5 +202,5 @@ end # Disable xHCI compliance mode - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" end diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb index fb9070f..abfbc0a 100644 --- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb @@ -31,7 +31,7 @@ register "prt0_gpio" = "GPIO_PRT0_UDEF" register "usb_config_override" = "1" - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index b4e627c..3102b1f 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -31,7 +31,7 @@ register "prt0_gpio" = "GPIO_PRT0_UDEF" register "usb_config_override" = "1" - register "DisableComplianceMode" = "1" + register "disable_compliance_mode" = "1" register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 57aa085..e3bfa1e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -607,7 +607,7 @@ /* * Options to disable XHCI Link Compliance Mode. */ - silconfig->DisableComplianceMode = cfg->DisableComplianceMode; + silconfig->DisableComplianceMode = cfg->disable_compliance_mode; /* * Options to change USB3 ModPhy setting for Integrated Filter value. diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 88ec1ff..c1bc020 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -184,7 +184,7 @@ * disable Compliance Mode. Set TRUE to disable Compliance Mode. * 0:FALSE(Default), 1:True. */ - uint8_t DisableComplianceMode; + uint8_t disable_compliance_mode; /* Options to change USB3 ModPhy setting for the Integrated Filter (IF) * value. Default is 0 to not changing default IF value (0x12). Set -- To view, visit https://review.coreboot.org/c/coreboot/+/75854?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d5605134a753f161a66857c7f78844ae7490cd6 Gerrit-Change-Number: 75854 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for PmicPmcIpcCtrl
by Jakub Czapiga (Code Review) 19 Jun '23

19 Jun '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75853?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/apollolake: Switch to snake case for PmicPmcIpcCtrl ...................................................................... soc/intel/apollolake: Switch to snake case for PmicPmcIpcCtrl For a unification of the naming convension, change from pascal case to snake case style for parameter 'PmicPmcIpcCtrl'. Change-Id: I3632d1e83108221d3487b4f175133ad347238bc5 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75853 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 3 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index c001dbe..fdfcd61 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -275,18 +275,18 @@ # RegOrValue (15:8): 0x2 and RegAndValue (7:0) 0xF8. # The register is defined as: D[7:3] RSVD, D[2:0] PWROKDELAY. # uint8 RegOrValue, RegAndValue, PmicReadReg - # RegOrValue = (UINT8)((PmicPmcIpcCtrl >> 8) & 0xff); - # RegAndValue = (UINT8)(PmicPmcIpcCtrl & 0xff); + # RegOrValue = (UINT8)((pmic_pmc_ipc_ctrl >> 8) & 0xff); + # RegAndValue = (UINT8)(pmic_pmc_ipc_ctrl & 0xff); # PmicReadReg &= RegAndValue; # PmicReadReg |= RegOrValue; # PmicReadReg value will be programmed into PMIC D[2:0] PWROKDELAY field # and D[7:3] RSVD will not be impacted. - # Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay + # Configure pmic_pmc_ipc_ctrl for PMC to program PMIC PCH_PWROK delay # from 100ms to 10ms. # PWROKDELAY[2:0]: 000=2.5ms, 001=5.0ms, 010=10ms, 011=15ms, 100=20ms, # 101=50ms, 110=75ms, 111=100ms (default) - register "PmicPmcIpcCtrl" = "0x5e4302f8" + register "pmic_pmc_ipc_ctrl" = "0x5e4302f8" # FSP UPD to modify the Integrated Filter (IF) value # Set it to default value: 0x12 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 76a6cc4..57aa085 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -602,7 +602,7 @@ * improve boot performance, configure PmicPmcIpcCtrl for PMC to program * PMIC PCH_PWROK delay. */ - silconfig->PmicPmcIpcCtrl = cfg->PmicPmcIpcCtrl; + silconfig->PmicPmcIpcCtrl = cfg->pmic_pmc_ipc_ctrl; /* * Options to disable XHCI Link Compliance Mode. diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index fa22415..88ec1ff 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -178,7 +178,7 @@ * Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address * (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0) */ - uint32_t PmicPmcIpcCtrl; + uint32_t pmic_pmc_ipc_ctrl; /* Options to disable XHCI Link Compliance Mode. Default is FALSE to not * disable Compliance Mode. Set TRUE to disable Compliance Mode. -- To view, visit https://review.coreboot.org/c/coreboot/+/75853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3632d1e83108221d3487b4f175133ad347238bc5 Gerrit-Change-Number: 75853 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for SataPortsHotPlug
by Jakub Czapiga (Code Review) 19 Jun '23

19 Jun '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75852?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/apollolake: Switch to snake case for SataPortsHotPlug ...................................................................... soc/intel/apollolake: Switch to snake case for SataPortsHotPlug For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsHotPlug'. Change-Id: I8fc8b30ac2c182ffaf2dee37e0116e27071b6a2c Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75852 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 9ec52b1..76a6cc4 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -689,7 +689,7 @@ if (cfg->emmc_host_max_speed != 0) silconfig->eMMCHostMaxSpeed = cfg->emmc_host_max_speed; - memcpy(silconfig->SataPortsHotPlug, cfg->SataPortsHotPlug, + memcpy(silconfig->SataPortsHotPlug, cfg->sata_ports_hot_plug, sizeof(silconfig->SataPortsHotPlug)); silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b956252..fa22415 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -104,7 +104,7 @@ uint8_t emmc_host_max_speed; /* Sata Ports Hot Plug */ - uint8_t SataPortsHotPlug[2]; + uint8_t sata_ports_hot_plug[2]; /* Sata Ports Enable */ uint8_t sata_ports_enable[2]; -- To view, visit https://review.coreboot.org/c/coreboot/+/75852?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fc8b30ac2c182ffaf2dee37e0116e27071b6a2c Gerrit-Change-Number: 75852 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: vc/intel/fsp/mtl: Update header files from 3194_81 to 3223.80
by Kilari Raasi (Code Review) 19 Jun '23

19 Jun '23

Kilari Raasi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75916?usp=email ) Change subject: vc/intel/fsp/mtl: Update header files from 3194_81 to 3223.80 ...................................................................... vc/intel/fsp/mtl: Update header files from 3194_81 to 3223.80 Update header files for FSP for Meteor Lake platform to version 3223_80, previous version being 3194_81. FSPM: 1. Add 'ROWHAMMER','RhSelect','McRefreshRate','Lfsr0Mask','Lfsr1Mask' UPDs 2. Add 'TmeExcludeBase','TmeExcludeSize','GenerateNewTmeKey' UPDs 3. Address offset changes BUG=b:287890130 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I4b8d0a3a87be7dc0d899298eb8e4e48905090e71 Signed-off-by: Kilari Raasi <kilari.raasi(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspProducerDataHeader.h M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h 2 files changed, 145 insertions(+), 107 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/75916/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspProducerDataHeader.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspProducerDataHeader.h index aa96b3a..9029296 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspProducerDataHeader.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspProducerDataHeader.h @@ -1,78 +1,80 @@ -/** @file - - Copyright (c) 2023, Intel Corporation. All rights reserved. - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -**/ -#ifndef _FSP_PRODUCER_DATA_HEADER_H_ -#define _FSP_PRODUCER_DATA_HEADER_H_ - -#include <Guid/FspHeaderFile.h> - -// -// FSP Header Data structure from FspHeader driver. -// -#pragma pack(1) -/// -/// FSP Producer Data Subtype - 1 -/// -typedef struct { - /// - /// Byte 0x00: Length of this FSP producer data type record. - /// - UINT16 Length; - /// - /// Byte 0x02: FSP producer data type. - /// - UINT8 Type; - /// - /// Byte 0x03: Revision of this FSP producer data type. - /// - UINT8 Revision; - /// - /// Byte 0x04: 4 byte field of RC version which is used to build this FSP image. - /// - UINT32 RcVersion; - /// - /// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM". - /// - UINT8 BuildTimeStamp[BUILD_TIME_STAMP_SIZE]; -} FSP_PRODUCER_DATA_TYPE1; - -/// -/// FSP Producer Data Subtype - 2 -/// -typedef struct { - /// - /// Byte 0x00: Length of this FSP producer data type record. - /// - UINT16 Length; - /// - /// Byte 0x02: FSP producer data type. - /// - UINT8 Type; - /// - /// Byte 0x03: Revision of this FSP producer data type. - /// - UINT8 Revision; - /// - /// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image. - /// - UINT8 MrcVersion [4]; -} FSP_PRODUCER_DATA_TYPE2; - -typedef struct { - FSP_INFO_HEADER FspInfoHeader; - FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader; - FSP_PRODUCER_DATA_TYPE1 FspProduceDataType1; - FSP_PRODUCER_DATA_TYPE2 FspProduceDataType2; - FSP_PATCH_TABLE FspPatchTable; -} FSP_PRODUCER_DATA_TABLES; -#pragma pack() - -#endif // _FSP_PRODUCER_DATA_HEADER_H +/** @file + + Copyright (c) 2023, Intel Corporation. All rights reserved. + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ +#ifndef _FSP_PRODUCER_DATA_HEADER_H_ +#define _FSP_PRODUCER_DATA_HEADER_H_ + +#include <Guid/FspHeaderFile.h> + +#define BUILD_TIME_STAMP_SIZE 12 + +// +// FSP Header Data structure from FspHeader driver. +// +#pragma pack(1) +/// +/// FSP Producer Data Subtype - 1 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of RC version which is used to build this FSP image. + /// + UINT32 RcVersion; + /// + /// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM". + /// + UINT8 BuildTimeStamp[BUILD_TIME_STAMP_SIZE]; +} FSP_PRODUCER_DATA_TYPE1; + +/// +/// FSP Producer Data Subtype - 2 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image. + /// + UINT8 MrcVersion [4]; +} FSP_PRODUCER_DATA_TYPE2; + +typedef struct { + FSP_INFO_HEADER FspInfoHeader; + FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader; + FSP_PRODUCER_DATA_TYPE1 FspProduceDataType1; + FSP_PRODUCER_DATA_TYPE2 FspProduceDataType2; + FSP_PATCH_TABLE FspPatchTable; +} FSP_PRODUCER_DATA_TABLES; +#pragma pack() + +#endif // _FSP_PRODUCER_DATA_HEADER_H diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h index aacb42a..c0424c7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h @@ -2197,9 +2197,11 @@ **/ UINT8 RMC; -/** Offset 0x0B82 - Reserved +/** Offset 0x0B82 - Row Hammering Prevention + Enables/Disable Row Hammering Prevention + $EN_DIS **/ - UINT8 Reserved55; + UINT8 ROWHAMMER; /** Offset 0x0B83 - Dimm ODT Training Enables/Disable Dimm ODT Training @@ -2233,7 +2235,7 @@ /** Offset 0x0B88 - Reserved **/ - UINT8 Reserved56[2]; + UINT8 Reserved55[2]; /** Offset 0x0B8A - DIMM CA ODT Training Enable/Disable DIMM CA ODT Training @@ -2243,7 +2245,7 @@ /** Offset 0x0B8B - Reserved **/ - UINT8 Reserved57[3]; + UINT8 Reserved56[3]; /** Offset 0x0B8E - Read Vref Decap Training Enable/Disable Read Vref Decap Training @@ -2265,7 +2267,7 @@ /** Offset 0x0B91 - Reserved **/ - UINT8 Reserved58[4]; + UINT8 Reserved57[4]; /** Offset 0x0B95 - Duty Cycle Correction Training Enable/Disable Duty Cycle Correction Training @@ -2275,7 +2277,7 @@ /** Offset 0x0B96 - Reserved **/ - UINT8 Reserved59[17]; + UINT8 Reserved58[17]; /** Offset 0x0BA7 - ECC Support Enables/Disable ECC Support @@ -2309,7 +2311,7 @@ /** Offset 0x0BB3 - Reserved **/ - UINT8 Reserved60; + UINT8 Reserved59; /** Offset 0x0BB4 - IbeccProtectedRegionBases IBECC Protected Region Bases per IBECC instance @@ -2387,9 +2389,11 @@ **/ UINT8 ThrtCkeMinDefeat; -/** Offset 0x0BEE - Reserved +/** Offset 0x0BEE - Row Hammer Select + Row Hammer Select + 0:Disable, 1:RFM, 2:pTRR **/ - UINT8 Reserved61; + UINT8 RhSelect; /** Offset 0x0BEF - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) @@ -2399,7 +2403,7 @@ /** Offset 0x0BF0 - Reserved **/ - UINT8 Reserved62[4]; + UINT8 Reserved60[4]; /** Offset 0x0BF4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP @@ -2658,7 +2662,7 @@ /** Offset 0x0C2B - Reserved **/ - UINT8 Reserved63[2]; + UINT8 Reserved61[2]; /** Offset 0x0C2D - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def) @@ -2676,9 +2680,11 @@ **/ UINT8 EnCmdRate; -/** Offset 0x0C30 - Reserved +/** Offset 0x0C30 - MC_REFRESH_RATE + Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh + 0:NORMAL Refresh, 1:1x Refresh, 2:2x Refresh, 3:4x Refresh **/ - UINT8 Reserved64; + UINT8 McRefreshRate; /** Offset 0x0C31 - Energy Performance Gain Enable/disable Energy Performance Gain. 0: Disable; 1: Enable @@ -2686,9 +2692,10 @@ **/ UINT8 EpgEnable; -/** Offset 0x0C32 - Reserved +/** Offset 0x0C32 - RH pTRR LFSR0 Mask + Row Hammer pTRR LFSR0 Mask, 1/2^(value) **/ - UINT8 Reserved65; + UINT8 Lfsr0Mask; /** Offset 0x0C33 - User Manual Threshold Disabled: Predefined threshold will be used.\n @@ -2706,7 +2713,7 @@ /** Offset 0x0C35 - Reserved **/ - UINT8 Reserved66; + UINT8 Reserved62; /** Offset 0x0C36 - Power Down Mode This option controls command bus tristating during idle periods @@ -2743,7 +2750,7 @@ /** Offset 0x0C3B - Reserved **/ - UINT8 Reserved67[8]; + UINT8 Reserved63[8]; /** Offset 0x0C43 - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. @@ -2758,7 +2765,7 @@ /** Offset 0x0C45 - Reserved **/ - UINT8 Reserved68; + UINT8 Reserved64; /** Offset 0x0C46 - Post Code Output Port This option configures Post Code Output Port @@ -2778,7 +2785,7 @@ /** Offset 0x0C4A - Reserved **/ - UINT8 Reserved69[2]; + UINT8 Reserved65[2]; /** Offset 0x0C4C - BCLK RFI Frequency Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No @@ -2821,7 +2828,16 @@ /** Offset 0x0C62 - Reserved **/ - UINT8 Reserved70[13]; + UINT8 Reserved66[11]; + +/** Offset 0x0C6D - RH pTRR LFSR1 Mask + Row Hammer pTRR LFSR1 Mask, 1/2^(value) +**/ + UINT8 Lfsr1Mask; + +/** Offset 0x0C6E - Reserved +**/ + UINT8 Reserved67; /** Offset 0x0C6F - Command Pins Mapping BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller @@ -2837,7 +2853,7 @@ /** Offset 0x0C71 - Reserved **/ - UINT8 Reserved71[24]; + UINT8 Reserved68[24]; /** Offset 0x0C89 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -2873,7 +2889,7 @@ /** Offset 0x0C8E - Reserved **/ - UINT8 Reserved72[2]; + UINT8 Reserved69[2]; /** Offset 0x0C90 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot @@ -2887,7 +2903,7 @@ /** Offset 0x0C95 - Reserved **/ - UINT8 Reserved73[143]; + UINT8 Reserved70[143]; /** Offset 0x0D24 - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -2903,7 +2919,7 @@ /** Offset 0x0D28 - Reserved **/ - UINT8 Reserved74[28]; + UINT8 Reserved71[28]; /** Offset 0x0D44 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -2919,7 +2935,7 @@ /** Offset 0x0D46 - Reserved **/ - UINT8 Reserved75[2]; + UINT8 Reserved72[2]; /** Offset 0x0D48 - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write @@ -2930,7 +2946,7 @@ /** Offset 0x0D49 - Reserved **/ - UINT8 Reserved76[34]; + UINT8 Reserved73[34]; /** Offset 0x0D6B - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI @@ -2983,7 +2999,7 @@ /** Offset 0x0D73 - Reserved **/ - UINT8 Reserved77[100]; + UINT8 Reserved74[100]; /** Offset 0x0DD7 - Avx2 Voltage Guardband Scaling Factor AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in @@ -3006,7 +3022,7 @@ /** Offset 0x0DDA - Reserved **/ - UINT8 Reserved78[2]; + UINT8 Reserved75[2]; /** Offset 0x0DDC - SerialIoUartDebugRxPinMux - FSPM Select RX pin muxing for SerialIo UART used for debug @@ -3032,7 +3048,27 @@ /** Offset 0x0DEC - Reserved **/ - UINT8 Reserved79[188]; + UINT8 Reserved76[164]; + +/** Offset 0x0E90 - TME Exclude Base Address + TME Exclude Base Address. +**/ + UINT64 TmeExcludeBase; + +/** Offset 0x0E98 - TME Exclude Size Value + TME Exclude Size Value. +**/ + UINT64 TmeExcludeSize; + +/** Offset 0x0EA0 - Generate New TME Key + Enable: Generate New TME Key, Disable(Default): TME key determine by type of reset + $EN_DIS +**/ + UINT8 GenerateNewTmeKey; + +/** Offset 0x0EA1 - Reserved +**/ + UINT8 Reserved77[7]; } FSP_M_CONFIG; /** Fsp M UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/75916?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b8d0a3a87be7dc0d899298eb8e4e48905090e71 Gerrit-Change-Number: 75916 Gerrit-PatchSet: 1 Gerrit-Owner: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/intel/mtlrvp: disable acpi timer for xtal shutdown
by Paul Menzel (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Nico Huber, Sukumar Ghorai. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75898?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/intel/mtlrvp: disable acpi timer for xtal shutdown ...................................................................... Patch Set 4: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75898/comment/d9191bc7_bac4470a : PS3, Line 9: acpi timer need to disable for xtal shutdown > Acknowledged You missed the *be*. https://review.coreboot.org/c/coreboot/+/75898/comment/1b75a1f3_29e67a4d : PS3, Line 9: acpi timer need to disable for xtal shutdown, requirement for : platform to enter deepest sleep s0i2.2. > https://review.coreboot.org/c/coreboot/+/75822/3/src/soc/intel/meteorlake/p…. […] Ok, thank you. It says it in that comment. It’d be great to have the datasheet name/section. Commit Message: https://review.coreboot.org/c/coreboot/+/75898/comment/e4afba72_fbd49ab1 : PS4, Line 11: How did you test this? Please add a TEST= line. Patchset: PS4: The Kconfig help text says: > This should be disabled for devices running on battery since > it can draw much power. Further, it must be disabled, if S0ix > is enabled. Can’t this be determined programmatically, if S0ix is supported or not? -- To view, visit https://review.coreboot.org/c/coreboot/+/75898?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib87b7555217b6954fca98f95b86d03016cd9b783 Gerrit-Change-Number: 75898 Gerrit-PatchSet: 4 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Comment-Date: Mon, 19 Jun 2023 11:07:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/meteorlake: Set Energy Perf Bias appropriate default value.
by Kapil Porwal (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Erin Park, Paul Menzel, Tarun Tuli. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75907?usp=email ) Change subject: soc/intel/meteorlake: Set Energy Perf Bias appropriate default value. ...................................................................... Patch Set 1: (1 comment) File src/include/cpu/x86/msr.h: https://review.coreboot.org/c/coreboot/+/75907/comment/efa59081_28331ba7 : PS1, Line 56: #define ENERGY_POLICY_BALANCE_POWERSAVE 8 > Please make that a separate commit und use tabs for alignment. +1, this file is not specific to Meteorlake. Please move it to a separate commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/75907?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib716584f516a538251c022e15b3193359b794366 Gerrit-Change-Number: 75907 Gerrit-PatchSet: 1 Gerrit-Owner: Erin Park <erin.park(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Erin Park <erin.park(a)intel.com> Gerrit-Comment-Date: Mon, 19 Jun 2023 11:04:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex: Fix PLD for USB type-A port
by Kapil Porwal (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Tarun Tuli. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75911?usp=email ) Change subject: mb/google/rex: Fix PLD for USB type-A port ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > please highlight if any problem we are fixing with this CL like a TEST line Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/75911?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3e76c11dd6808eee4c9c2f3f71604a60379b5a5 Gerrit-Change-Number: 75911 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Mon, 19 Jun 2023 10:46:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex: Fix PLD for USB type-A port
by Kapil Porwal (Code Review) 19 Jun '23

19 Jun '23

Attention is currently required from: Kapil Porwal, Tarun Tuli. Hello Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75911?usp=email to look at the new patch set (#3). Change subject: mb/google/rex: Fix PLD for USB type-A port ...................................................................... mb/google/rex: Fix PLD for USB type-A port USB type-A port with same PLD.token information as USB type-C port, causes conflict while generating ACPI code for the EC CONN device. Use a different PLD.token number for type-A port to fix the issue. BUG=b:286328285 TEST=check ACPI can have right USB port in EC CON. before patch: Package (0x02) { "usb2-port", \_SB.PCI0.XHCI.RHUB.HS01 }, Package (0x02) { "usb3-port", \_SB.PCI0.TXHC.RHUB.SS01 }, after patch: Package (0x02) { "usb2-port", \_SB.PCI0.XHCI.RHUB.HS01 }, Package (0x02) { "usb3-port", \_SB.PCI0.TXHC.RHUB.SS03 }, Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: If3e76c11dd6808eee4c9c2f3f71604a60379b5a5 --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/75911/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/75911?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3e76c11dd6808eee4c9c2f3f71604a60379b5a5 Gerrit-Change-Number: 75911 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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