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Change subject: mb/google/rex: Fix PLD for USB type-A port
......................................................................
mb/google/rex: Fix PLD for USB type-A port
BUG=b:286328285
TEST=check ACPI can have right USB port in EC CON.
before patch:
Package (0x02)
{
"usb2-port",
\_SB.PCI0.XHCI.RHUB.HS01
},
Package (0x02)
{
"usb3-port",
\_SB.PCI0.TXHC.RHUB.SS01
},
after patch:
Package (0x02)
{
"usb2-port",
\_SB.PCI0.XHCI.RHUB.HS01
},
Package (0x02)
{
"usb3-port",
\_SB.PCI0.TXHC.RHUB.SS03
},
Signed-off-by: Kapil Porwal <kapilporwal(a)google.com>
Change-Id: If3e76c11dd6808eee4c9c2f3f71604a60379b5a5
---
M src/mainboard/google/rex/variants/rex0/overridetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/75911/2
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Change subject: mb/google/hades: Update typeC usb PLD
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brya/variants/hades/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/75912/comment/20aeb037_6f645589 :
PS3, Line 292: RIGHT
You need to duplicate PLD data between tcss_usb3_port`X` and corresponding usb2_port`Y`. `BACK` as panel doesn't look correct for hades.
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Change subject: mb/google/rex/var/screebo: Remove rp2 and add rp1/rp3
......................................................................
Patch Set 8: Code-Review+2
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Change subject: soc/amd/common/block/noncar: Merge romstage into bootblock
......................................................................
Patch Set 20: Code-Review+1
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Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
......................................................................
Patch Set 14: Code-Review+2
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Change subject: soc/amd/common/iommu.c: Make sure iommu is enabled
......................................................................
soc/amd/common/iommu.c: Make sure iommu is enabled
Don't rely on vendorcode to set enable bit on IOMMU.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Signed-off-by: Naresh Solanki <Naresh.Solanki(a)9elements.com>
Change-Id: I1805a20656b7fb3915f8cc93c618ee074461840f
---
M src/soc/amd/common/block/iommu/iommu.c
1 file changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/75829/6
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Change subject: soc/amd/common/iommu.c: Make sure iommu is enabled
......................................................................
Patch Set 5:
(3 comments)
File src/soc/amd/common/block/iommu/iommu.c:
https://review.coreboot.org/c/coreboot/+/75829/comment/670488c8_2bc0befe :
PS3, Line 21: res->flags = IORESOURCE_MEM;
> probably something for a separate patch, but shouldn't we add IORESOURCE_PCI64 here too, so that the upper register will also be written by pci_dev_set_resources?
IVRS generation requires access to MMIO region. So this would break 32B code or 64B code without the upper regions mapped (Currently the case).
https://review.coreboot.org/c/coreboot/+/75829/comment/3cf3b01d_609dea7a :
PS3, Line 27: 0x44
> would be good to have a define for the iommu pci config space registers 0x44 and 0x48
Done
https://review.coreboot.org/c/coreboot/+/75829/comment/72cfce4e_967a7b74 :
PS3, Line 28: 1
> would be good to have a define for the iommu enable bit
Done
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Change subject: soc/amd/common/iommu.c: Make sure iommu is enabled
......................................................................
soc/amd/common/iommu.c: Make sure iommu is enabled
Don't rely on vendorcode to set enable bit on IOMMU.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Signed-off-by: Naresh Solanki <Naresh.Solanki(a)9elements.com>
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---
M src/soc/amd/common/block/iommu/iommu.c
1 file changed, 13 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/75829/5
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Change subject: soc/amd/common/iommu.c: Make sure iommu is enabled
......................................................................
soc/amd/common/iommu.c: Make sure iommu is enabled
Don't rely on vendorcode to set enable bit on IOMMU.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Signed-off-by: Naresh Solanki <Naresh.Solanki(a)9elements.com>
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---
M src/soc/amd/common/block/iommu/iommu.c
1 file changed, 12 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/75829/4
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