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Change subject: mb/google/rex/var/screebo: Change rp0/rp2 to rp1/rp3
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Patch Set 7: Code-Review+2
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Change subject: ec/google/chromeec: Use mux_conn to get the right USB port
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Abandoned
no need not the root cause
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Change subject: mb/google/rex: Fix PLD for USB type-A port
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Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
please highlight if any problem we are fixing with this CL like a TEST line
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Change subject: mb/google/hades: Update typeC usb PLD
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Patch Set 3:
(1 comment)
Patchset:
PS3:
This is fix the ACPI but the kernel seems not right.
[ 5.488814] typec port0: bound usb2-port3 (ops 0xffffffffa3200b18)
[ 5.503801] typec port1: bound usb2-port1 (ops 0xffffffffa3200b18)
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Change subject: mainboard/google/rex: Enable crashlog
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Patch Set 18:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74770/comment/158beb3e_5174fa51 :
PS18, Line 10: shared_sram
please mention which SRAM is for IOE and PMC
https://review.coreboot.org/c/coreboot/+/74770/comment/b6f6182e_0196ec58 :
PS18, Line 13: Bug
BUG
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Change subject: mainboard/google/rex: Enable crashlog
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Patch Set 18:
(4 comments)
Patchset:
PS18:
wondering why these CLs are not build test atleast ?
PS18:
> if not, just ignore this
Acknowledged
File src/mainboard/google/rex/variants/rex0/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/74770/comment/a694446c_eaef408b :
PS18, Line 838: device shared_sram2 on end
device ref shared_sram2 on end <--- move this line at 352
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PS18, Line 839: device shared_sram on end
device ref shared_sram on end <--- move this line at 415
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Change subject: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable devicetree option
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Patch Set 4: Code-Review+1
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Change subject: soc/intel/meteorlake: Add support for crashlog
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Patch Set 24:
(1 comment)
Patchset:
PS23:
> 1. I don’t see any redundant entries.
can you please share your AP log (similar one that i have pasted here)
```
[DEBUG] Region[0x0].Tag=0x7 offset=0x9b, size=0x400
[DEBUG] Region[0x1].Tag=0x0 offset=0xa00, size=0x280
[DEBUG] Region[0x2].Tag=0x0 offset=0x2bb0, size=0xa
[DEBUG] Region[0x3].Tag=0x0 offset=0x3a00, size=0x80
[DEBUG] Region[0x4].Tag=0x1 offset=0x780, size=0x280
[DEBUG] Region[0x5].Tag=0x1 offset=0x12d8, size=0xa
[DEBUG] Region[0x6].Tag=0x1 offset=0x1600, size=0x6e
[DEBUG] Region[0x7].Tag=0x0 offset=0x0, size=0x0
[DEBUG] Region[0x0].Tag=0x7 offset=0x9b, size=0x400
[DEBUG] Region[0x1].Tag=0x0 offset=0xa00, size=0x280
[DEBUG] Region[0x2].Tag=0x0 offset=0x2bb0, size=0xa
[DEBUG] Region[0x3].Tag=0x0 offset=0x3a00, size=0x80
[DEBUG] Region[0x4].Tag=0x1 offset=0x780, size=0x280
[DEBUG] Region[0x5].Tag=0x1 offset=0x12d8, size=0xa
[DEBUG] Region[0x6].Tag=0x1 offset=0x1600, size=0x6e
```
my question is how to understand from the above entry which one is for SOC.PMC and IOE.PMC?
>
> in crashlog.h
> #define CRASHLOG_DESCRIPTOR_TABLE_TAG_SOC 0x0
> #define CRASHLOG_DESCRIPTOR_TABLE_TAG_IOE 0x1
>
> We parse descriptor table to learn about crashlog records in SOC PMC, and OIE PMC SRAM. Both data has different tags. Tag=7 contain BDF info for IOE PMC SRAM device, but since we already define it in header (#define PCI_DEV_IOE_SRAM) i don’t parse the tag=7. We parse descriptor table entries with tag=0 and tag=1 only. In first pass we collect SOC PMC crashlog records and also count IOE PMC records. This is needed to allocate right size of cbmem for IOE crashlog data. After this parsing i allocate CBMEM for IOE crashlog and parse descriptor table again to collect IOE crashlog data.
>
> 2. while copying data from SRAM, we ignore invalid crashlog entries. So the final size of crashlog is adjusted.
thanks
>
> 3. that is coming from common code, pushed another patch.
+2'ed
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Change subject: soc/intel/common: Print crashlog size info in hex
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Patch Set 4: Code-Review+2
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