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Hello Felix Singer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: commonlib/console/post_code.h: Change post code prefix to POSTCODE
......................................................................
commonlib/console/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' src/commonlib/include/commonlib/console/post_codes.h
myArray=`grep -e "^#define POSTCODE_" src/commonlib/include/commonlib/console/post_codes.h | grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`
for str in ${myArray[@]}; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r POST_$splitstr src | cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"
done
Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Signed-off-by: lilacious <yuchenhe126(a)gmail.com>
---
M src/arch/x86/acpi_s3.c
M src/arch/x86/c_start.S
M src/arch/x86/postcar_loader.c
M src/arch/x86/tables.c
M src/commonlib/include/commonlib/console/post_codes.h
M src/cpu/intel/car/core2/cache_as_ram.S
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/p3/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/qemu-x86/cache_as_ram_bootblock.S
M src/cpu/x86/entry16.S
M src/cpu/x86/entry32.S
M src/device/device.c
M src/device/pci_device.c
M src/drivers/amd/agesa/cache_as_ram.S
M src/drivers/intel/fsp1_1/cache_as_ram.S
M src/drivers/intel/fsp1_1/car.c
M src/drivers/intel/fsp1_1/fsp_util.c
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/notify.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/drivers/pc80/rtc/post.c
M src/ec/google/wilco/commands.c
M src/lib/hardwaremain.c
M src/lib/prog_loaders.c
M src/lib/ramtest.c
M src/northbridge/intel/haswell/broadwell_mrc/raminit.c
M src/northbridge/intel/haswell/haswell_mrc/raminit.c
M src/northbridge/intel/i440bx/raminit.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/security/tpm/tspi/tspi.c
M src/security/vboot/vboot_logic.c
M src/soc/amd/cezanne/cpu.c
M src/soc/amd/common/block/cpu/car/cache_as_ram.S
M src/soc/amd/common/block/cpu/noncar/pre_c.S
M src/soc/amd/common/block/cpu/smm/finalize.c
M src/soc/amd/glinda/cpu.c
M src/soc/amd/mendocino/cpu.c
M src/soc/amd/phoenix/cpu.c
M src/soc/amd/picasso/cpu.c
M src/soc/amd/stoneyridge/cpu.c
M src/soc/intel/alderlake/finalize.c
M src/soc/intel/baytrail/romstage/raminit.c
M src/soc/intel/broadwell/finalize.c
M src/soc/intel/broadwell/raminit.c
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/finalize.c
M src/soc/intel/common/acpi/platform.asl
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/p2sb/p2sblib.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/elkhartlake/finalize.c
M src/soc/intel/jasperlake/finalize.c
M src/soc/intel/meteorlake/chip.c
M src/soc/intel/meteorlake/finalize.c
M src/soc/intel/skylake/finalize.c
M src/soc/intel/tigerlake/finalize.c
M src/soc/intel/xeon_sp/finalize.c
M src/southbridge/intel/common/finalize.c
M src/southbridge/intel/i82801gx/lpc.c
M src/vendorcode/google/chromeos/cr50_enable_update.c
67 files changed, 180 insertions(+), 180 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/76043/2
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Gerrit-Change-Number: 76043
Gerrit-PatchSet: 2
Gerrit-Owner: Yuchen He <yuchenhe126(a)gmail.com>
Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Attention: Yuchen He <yuchenhe126(a)gmail.com>
Gerrit-MessageType: newpatchset
Yuchen He has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76043?usp=email )
Change subject: commonlib/console/post_code.h: Change post code prefix to POSTCODE
......................................................................
commonlib/console/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE.
The file was changed by running the following command from the top
level directory.
sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' src/commonlib/include/commonlib/console/post_codes.h
Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Signed-off-by: lilacious <yuchenhe126(a)gmail.com>
---
M src/commonlib/include/commonlib/console/post_codes.h
1 file changed, 61 insertions(+), 61 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/76043/1
diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h
index a8a8d95..0c96ee5 100644
--- a/src/commonlib/include/commonlib/console/post_codes.h
+++ b/src/commonlib/include/commonlib/console/post_codes.h
@@ -31,7 +31,7 @@
* \brief Not an actual post-code - used to clear port80h
*
*/
-#define POST_CODE_CLEAR 0x00
+#define POSTCODE_CODE_CLEAR 0x00
/**
* \brief Entry into 'crt0.s'. reset code jumps to here
@@ -39,7 +39,7 @@
* First instruction that gets executed after the reset vector jumps.
* This indicates that the reset vector points to the correct code segment.
*/
-#define POST_RESET_VECTOR_CORRECT 0x01
+#define POSTCODE_RESET_VECTOR_CORRECT 0x01
/**
* \brief Entry into protected mode
@@ -47,14 +47,14 @@
* Preparing to enter protected mode. This is POSTed right before changing to
* protected mode.
*/
-#define POST_ENTER_PROTECTED_MODE 0x10
+#define POSTCODE_ENTER_PROTECTED_MODE 0x10
/**
* \brief Start copying coreboot to RAM with decompression if compressed
*
* POSTed before ramstage is about to be loaded into memory
*/
-#define POST_PREPARE_RAMSTAGE 0x11
+#define POSTCODE_PREPARE_RAMSTAGE 0x11
/**
* \brief Copy/decompression finished; jumping to RAM
@@ -62,34 +62,34 @@
* This is called after ramstage is loaded in memory, and before
* the code jumps there. This represents the end of romstage.
*/
-#define POST_RAMSTAGE_IS_PREPARED 0x12
+#define POSTCODE_RAMSTAGE_IS_PREPARED 0x12
/**
* \brief Entry into c_start
*
* c_start.S is the first code executing in ramstage.
*/
-#define POST_ENTRY_C_START 0x13
+#define POSTCODE_ENTRY_C_START 0x13
/**
* \brief Entry into bootblock cache-as-RAM code
*
*/
-#define POST_BOOTBLOCK_CAR 0x21
+#define POSTCODE_BOOTBLOCK_CAR 0x21
/**
* \brief Entry into pci_scan_bus
*
* Entered pci_scan_bus()
*/
-#define POST_ENTER_PCI_SCAN_BUS 0x24
+#define POSTCODE_ENTER_PCI_SCAN_BUS 0x24
/**
* \brief Entry into pci_scan_bus
*
* Entered pci_scan_bus()
*/
-#define POST_EXIT_PCI_SCAN_BUS 0x25
+#define POSTCODE_EXIT_PCI_SCAN_BUS 0x25
/**
* \brief Pre-memory init preparation start
@@ -97,7 +97,7 @@
* Post code emitted in romstage before making callbacks to allow SoC/mainboard
* to prepare params for FSP memory init.
*/
-#define POST_MEM_PREINIT_PREP_START 0x34
+#define POSTCODE_MEM_PREINIT_PREP_START 0x34
/**
* \brief Pre-memory init preparation end
@@ -105,14 +105,14 @@
* Post code emitted in romstage after returning from SoC/mainboard callbacks
* to prepare params for FSP memory init.
*/
-#define POST_MEM_PREINIT_PREP_END 0x36
+#define POSTCODE_MEM_PREINIT_PREP_END 0x36
/**
* \brief Console is initialized
*
* The console is initialized and is ready for usage
*/
-#define POST_CONSOLE_READY 0x39
+#define POSTCODE_CONSOLE_READY 0x39
/**
* \brief Console boot message succeeded
@@ -120,21 +120,21 @@
* First console message has been successfully sent through the console backend
* driver.
*/
-#define POST_CONSOLE_BOOT_MSG 0x40
+#define POSTCODE_CONSOLE_BOOT_MSG 0x40
/**
* \brief Before enabling the cache
*
* Going to enable the cache
*/
-#define POST_ENABLING_CACHE 0x60
+#define POSTCODE_ENABLING_CACHE 0x60
/**
* \brief Pre call to RAM stage main()
*
* POSTed right before RAM stage main() is called from c_start.S
*/
-#define POST_PRE_HARDWAREMAIN 0x6e
+#define POSTCODE_PRE_HARDWAREMAIN 0x6e
/**
* \brief Entry into coreboot in RAM stage main()
@@ -142,238 +142,238 @@
* This is the first call in hardwaremain.c. If this code is POSTed, then
* ramstage has successfully loaded and started executing.
*/
-#define POST_ENTRY_HARDWAREMAIN 0x6f
+#define POSTCODE_ENTRY_HARDWAREMAIN 0x6f
/**
* \brief Before Device Probe
*
* Boot State Machine: bs_pre_device()
*/
-#define POST_BS_PRE_DEVICE 0x70
+#define POSTCODE_BS_PRE_DEVICE 0x70
/**
* \brief Initializing Chips
*
* Boot State Machine: bs_dev_init_chips()
*/
-#define POST_BS_DEV_INIT_CHIPS 0x71
+#define POSTCODE_BS_DEV_INIT_CHIPS 0x71
/**
* \brief Starting Device Enumeration
*
* Boot State Machine: bs_dev_enumerate()
*/
-#define POST_BS_DEV_ENUMERATE 0x72
+#define POSTCODE_BS_DEV_ENUMERATE 0x72
/**
* \brief Device Resource Allocation
*
* Boot State Machine: bs_dev_resources()
*/
-#define POST_BS_DEV_RESOURCES 0x73
+#define POSTCODE_BS_DEV_RESOURCES 0x73
/**
* \brief Device Enable
*
* Boot State Machine: bs_dev_enable()
*/
-#define POST_BS_DEV_ENABLE 0x74
+#define POSTCODE_BS_DEV_ENABLE 0x74
/**
* \brief Device Initialization
*
* Boot State Machine: bs_dev_init()
*/
-#define POST_BS_DEV_INIT 0x75
+#define POSTCODE_BS_DEV_INIT 0x75
/**
* \brief After Device Probe
*
* Boot State Machine: bs_post_device()
*/
-#define POST_BS_POST_DEVICE 0x76
+#define POSTCODE_BS_POST_DEVICE 0x76
/**
* \brief OS Resume Check
*
* Boot State Machine: bs_os_resume_check()
*/
-#define POST_BS_OS_RESUME_CHECK 0x77
+#define POSTCODE_BS_OS_RESUME_CHECK 0x77
/**
* \brief OS Resume
*
* Boot State Machine: bs_os_resume()
*/
-#define POST_BS_OS_RESUME 0x78
+#define POSTCODE_BS_OS_RESUME 0x78
/**
* \brief Write Tables
*
* Boot State Machine: bs_write_tables()
*/
-#define POST_BS_WRITE_TABLES 0x79
+#define POSTCODE_BS_WRITE_TABLES 0x79
/**
* \brief Load Payload
*
* Boot State Machine: bs_payload_load()
*/
-#define POST_BS_PAYLOAD_LOAD 0x7a
+#define POSTCODE_BS_PAYLOAD_LOAD 0x7a
/**
* \brief Boot Payload
*
* Boot State Machine: bs_payload_boot()
*/
-#define POST_BS_PAYLOAD_BOOT 0x7b
+#define POSTCODE_BS_PAYLOAD_BOOT 0x7b
/**
* \brief Before calling FSP Notify (end of firmware)
*
* Going to call into FSP binary for Notify phase (end of firmware)
*/
-#define POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE 0x88
+#define POSTCODE_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE 0x88
/**
* \brief After calling FSP Notify (end of firmware)
*
* Going to call into FSP binary for Notify phase (end of firmware)
*/
-#define POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE 0x89
+#define POSTCODE_FSP_NOTIFY_AFTER_END_OF_FIRMWARE 0x89
/**
* \brief Before calling FSP TempRamInit
*
* Going to call into FSP binary for TempRamInit phase
*/
-#define POST_FSP_TEMP_RAM_INIT 0x90
+#define POSTCODE_FSP_TEMP_RAM_INIT 0x90
/**
* \brief Before calling FSP TempRamExit
*
* Going to call into FSP binary for TempRamExit phase
*/
-#define POST_FSP_TEMP_RAM_EXIT 0x91
+#define POSTCODE_FSP_TEMP_RAM_EXIT 0x91
/**
* \brief Before calling FSP MemoryInit
*
* Going to call into FSP binary for MemoryInit phase
*/
-#define POST_FSP_MEMORY_INIT 0x92
+#define POSTCODE_FSP_MEMORY_INIT 0x92
/**
* \brief Before calling FSP SiliconInit
*
* Going to call into FSP binary for SiliconInit phase
*/
-#define POST_FSP_SILICON_INIT 0x93
+#define POSTCODE_FSP_SILICON_INIT 0x93
/**
* \brief Before calling FSP Notify (after PCI enumeration)
*
* Going to call into FSP binary for Notify phase (after PCI enumeration)
*/
-#define POST_FSP_NOTIFY_BEFORE_ENUMERATE 0x94
+#define POSTCODE_FSP_NOTIFY_BEFORE_ENUMERATE 0x94
/**
* \brief Before calling FSP Notify (ready to boot)
*
* Going to call into FSP binary for Notify phase (ready to boot)
*/
-#define POST_FSP_NOTIFY_BEFORE_FINALIZE 0x95
+#define POSTCODE_FSP_NOTIFY_BEFORE_FINALIZE 0x95
/**
* \brief Indicate OS _PTS entry
*
* Called from _PTS asl method
*/
-#define POST_OS_ENTER_PTS 0x96
+#define POSTCODE_OS_ENTER_PTS 0x96
/**
* \brief Indicate OS _WAK entry
*
* Called from within _WAK method
*/
-#define POST_OS_ENTER_WAKE 0x97
+#define POSTCODE_OS_ENTER_WAKE 0x97
/**
* \brief After calling FSP MemoryInit
*
* FSP binary returned from MemoryInit phase
*/
-#define POST_FSP_MEMORY_EXIT 0x98
+#define POSTCODE_FSP_MEMORY_EXIT 0x98
/**
* \brief After calling FSP SiliconInit
*
* FSP binary returned from SiliconInit phase
*/
-#define POST_FSP_SILICON_EXIT 0x99
+#define POSTCODE_FSP_SILICON_EXIT 0x99
/**
* \brief Entry to write_pirq_table
*
* coreboot entered write_pirq_table
*/
-#define POST_X86_WRITE_PIRQ_TABLE 0x9a
+#define POSTCODE_X86_WRITE_PIRQ_TABLE 0x9a
/**
* \brief Entry to write_mptable
*
* coreboot entered write_mptable
*/
-#define POST_X86_WRITE_MPTABLE 0x9b
+#define POSTCODE_X86_WRITE_MPTABLE 0x9b
/**
* \brief Entry to write_acpi_table
*
* coreboot entered write_acpi_table
*/
-#define POST_X86_WRITE_ACPITABLE 0x9c
+#define POSTCODE_X86_WRITE_ACPITABLE 0x9c
/**
* \brief Before calling FSP Multiphase SiliconInit
*
* Going to call into FSP binary for Multiple phase SI Init
*/
-#define POST_FSP_MULTI_PHASE_SI_INIT_ENTRY 0xa0
+#define POSTCODE_FSP_MULTI_PHASE_SI_INIT_ENTRY 0xa0
/**
* \brief After calling FSP Multiphase SiliconInit
*
* FSP binary returned from Multiple phase SI Init
*/
-#define POST_FSP_MULTI_PHASE_SI_INIT_EXIT 0xa1
+#define POSTCODE_FSP_MULTI_PHASE_SI_INIT_EXIT 0xa1
/**
* \brief After calling FSP Notify (after PCI enumeration)
*
* Going to call into FSP binary for Notify phase (after PCI enumeration)
*/
-#define POST_FSP_NOTIFY_AFTER_ENUMERATE 0xa2
+#define POSTCODE_FSP_NOTIFY_AFTER_ENUMERATE 0xa2
/**
* \brief After calling FSP Notify (ready to boot)
*
* Going to call into FSP binary for Notify phase (ready to boot)
*/
-#define POST_FSP_NOTIFY_AFTER_FINALIZE 0xa3
+#define POSTCODE_FSP_NOTIFY_AFTER_FINALIZE 0xa3
/**
* \brief Invalid or corrupt ROM
*
* Set if firmware failed to find or validate a resource that is stored in ROM.
*/
-#define POST_INVALID_ROM 0xe0
+#define POSTCODE_INVALID_ROM 0xe0
/**
* \brief Invalid or corrupt CBFS
*
* Set if firmware failed to find or validate a resource that is stored in CBFS.
*/
-#define POST_INVALID_CBFS 0xe1
+#define POSTCODE_INVALID_CBFS 0xe1
/**
* \brief Vendor binary error
@@ -381,7 +381,7 @@
* Set if firmware failed to find or validate a vendor binary, or the binary
* generated a fatal error.
*/
-#define POST_INVALID_VENDOR_BINARY 0xe2
+#define POSTCODE_INVALID_VENDOR_BINARY 0xe2
/**
* \brief RAM failure
@@ -389,28 +389,28 @@
* Set if RAM could not be initialized. This includes RAM is missing,
* unsupported RAM configuration, or RAM failure.
*/
-#define POST_RAM_FAILURE 0xe3
+#define POSTCODE_RAM_FAILURE 0xe3
/**
* \brief Hardware initialization failure
*
* Set when a required hardware component was not found or is unsupported.
*/
-#define POST_HW_INIT_FAILURE 0xe4
+#define POSTCODE_HW_INIT_FAILURE 0xe4
/**
* \brief Video failure
*
* Video subsystem failed to initialize.
*/
-#define POST_VIDEO_FAILURE 0xe5
+#define POSTCODE_VIDEO_FAILURE 0xe5
/**
* \brief TPM failure
*
* An error with the TPM, either unexpected state or communications failure.
*/
-#define POST_TPM_FAILURE 0xed
+#define POSTCODE_TPM_FAILURE 0xed
/**
* \brief Not supposed to get here
@@ -419,7 +419,7 @@
*
* Check the console output for details.
*/
-#define POST_DEAD_CODE 0xee
+#define POSTCODE_DEAD_CODE 0xee
/**
* \brief Resume from suspend failed
@@ -427,7 +427,7 @@
* This post code is sent when the firmware is expected to resume it is
* unable to do so.
*/
-#define POST_RESUME_FAILURE 0xef
+#define POSTCODE_RESUME_FAILURE 0xef
/**
* \brief Jumping to payload
@@ -435,7 +435,7 @@
* Called right before jumping to a payload. If the boot sequence stops with
* this code, chances are the payload freezes.
*/
-#define POST_JUMPING_TO_PAYLOAD 0xf3
+#define POSTCODE_JUMPING_TO_PAYLOAD 0xf3
/**
* \brief Entry into elf boot
@@ -443,21 +443,21 @@
* This POST code is called right before invoking jmp_to_elf_entry()
* jmp_to_elf_entry() invokes the payload, and should never return
*/
-#define POST_ENTER_ELF_BOOT 0xf8
+#define POSTCODE_ENTER_ELF_BOOT 0xf8
/**
* \brief Final code before OS resumes
*
* Called right before jumping to the OS resume vector.
*/
-#define POST_OS_RESUME 0xfd
+#define POSTCODE_OS_RESUME 0xfd
/**
* \brief Final code before OS boots
*
* This may not be called depending on the payload used.
*/
-#define POST_OS_BOOT 0xfe
+#define POSTCODE_OS_BOOT 0xfe
/**
* \brief Elfload fail or die() called
@@ -474,6 +474,6 @@
* \n
* Check the console output to see exactly where the failure occurred.
*/
-#define POST_DIE 0xff
+#define POSTCODE_DIE 0xff
#endif /* POST_CODES_H */
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Change subject: mb/google/brya/acpi: Set polling timing for DL23 and LD23 to 2ms
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/google/brya/acpi: Set power down delay to 2ms after PEXVDD
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76051/comment/5106d054_7d5e365f :
PS3, Line 15: Signed-off-by: Tarun Tuli <taruntuli(a)google.com>
Signed-off line is usually grouped in Change-Id section.
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Change subject: mb/google/brya/acpi: Don't wait for PG in GPU off sequences
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Patch Set 3: Code-Review+1
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Change subject: mb/google/brya/var/vell: update FW_config to sync config.star
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Patch Set 4: Code-Review+1
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Change subject: mb/google/kahlee: Add EC_HOST_EVENT_PANIC to SCI mask
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75323/comment/20909995_1b121d16 :
PS2, Line 15: BRANCH=firmware-octopus-11297.B
> Should be Grunt branch?
Yep. Thank you.
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Hello Edward Hill, Edward Hill, Jason Nien, Karthik Ramasubramanian, Martin Roth, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75323?usp=email
to look at the new patch set (#3).
Change subject: mb/google/kahlee: Add EC_HOST_EVENT_PANIC to SCI mask
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mb/google/kahlee: Add EC_HOST_EVENT_PANIC to SCI mask
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the
Kernel when an EC panic occurs. If system safe mode is also enabled
on the EC, the kernel will have a short period to extract and save info
about the EC panic.
BUG=b:283245785
BRANCH=firmware-grunt-11031.B
TEST=Observe kernel ec panic handler run when ec panics
Change-Id: I8eeb5c0935d0531c21bcf4cd3d4fd9dc80b54f79
Signed-off-by: Rob Barnes <robbarnes(a)google.com>
---
M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/75323/3
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Change subject: mb/google/kahlee: Add EC_HOST_EVENT_PANIC to SCI mask
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Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75323/comment/56eca00f_a5079edb :
PS2, Line 15: BRANCH=firmware-octopus-11297.B
Should be Grunt branch?
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Gerrit-Comment-Date: Wed, 21 Jun 2023 20:34:57 +0000
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Yuchen He has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75809?usp=email )
Change subject: soc/amd/common/psp_verstage: move post codes to own header
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Patch Set 3:
(1 comment)
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https://review.coreboot.org/c/coreboot/+/75809/comment/8e1bc174_cfd6b9e8 :
PS2, Line 10: header away from unrelated code.
> For completeness, please mention that the new header file is included in the other one so that the c […]
Done
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