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Change subject: mb/google/brya/acpi: Set polling timing for DL23 and LD23 to 2ms
......................................................................
Patch Set 3:
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Change subject: mb/google/brya: Add support for variant_memcfg_init()
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/brya/acpi: Set power down delay to 2ms after PEXVDD
......................................................................
Patch Set 2:
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Subrata Banik has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/75998?usp=email )
Change subject: soc/intel/common/block/cse: Retrieve CSE RW FW version conditionally
......................................................................
soc/intel/common/block/cse: Retrieve CSE RW FW version conditionally
This patch introduces a newer config to store the CSE RW FW version into
the CBMEM. Prior to that CSE RW FW version was fetched unconditionally
and ended up increasing the boot time by 7ms to 20ms depending on the
SoC arch (including CSE arch).
The way to retrieve the CSE firmware version is by sending the HECI
command to read the CSE Boot Partition (BP) info. The cost of sending
HECI command to read the CSE FW version is between 7ms-20ms (depending
on the SoC architecture) hence,ensure this feature is platform specific
and only enabled for the platformthat would like to store the CSE version into the CBMEM.
TEST=Build and boot google/rex to avoid getting CSE RW FW version
to save 18ms of the boot time.
w/o this patch:
 10:start of ramstage               722,215 (43)
 17:starting LZ4 decompress (ignore for x86)   741,415 (19,200)
w/ this patch:
 10:start of ramstage               722,257 (43)
 17:starting LZ4 decompress (ignore for x86)   723,777 (1,520)
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I94f9f0f99706724c7d7e05668390f3deb603bd32
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/cse/cse_lite.c
3 files changed, 20 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/75998/2
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Change subject: mb/google/brya/acpi: Don't wait for PG in GPU off sequences
......................................................................
Patch Set 2:
This change is ready for review.
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75998?usp=email )
Change subject: soc/intel/common/block/cse: Retrieve CSE RW FW version conditionally
......................................................................
soc/intel/common/block/cse: Retrieve CSE RW FW version conditionally
This patch introduces a newer config to store the CSE RW FW version into
the CBMEM. Prior to that CSE RW FW version was fetched unconditionally
and ended up increasing the boot time by 7ms to 20ms depending on the
SoC arch (including CSE arch).
The way to retrieve the CSE firmware version is by sending the HECI
command to read the CSE Boot Partition (BP) info. The cost of sending
HECI command to read the CSE FW version is between 7ms-20ms (depending
on the SoC architecture) hence,ensure this feature is platform specific
and only enabled for the platformthat would like to store the CSE version
into the CBMEM.
TEST=Build and boot google/rex to avoid getting CSE RW FW version to save
18ms of the boot time.
w/o this patch:
 10:start of ramstage                 722,215 (43)
 17:starting LZ4 decompress (ignore for x86)      741,415 (19,200)
w/ this patch:
 10:start of ramstage                 722,257 (43)
 17:starting LZ4 decompress (ignore for x86)      723,777 (1,520)
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I94f9f0f99706724c7d7e05668390f3deb603bd32
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/cse/cse_lite.c
3 files changed, 20 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/75998/1
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index 876ec51..dc53268 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -45,6 +45,23 @@
Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented)
to make `HECI1` device disable using private configuration register (PCR) write.
+config SOC_INTEL_STORE_CSE_FW_VERSION
+ bool
+ default n
+ depends on SOC_INTEL_CSE_LITE_SKU
+ help
+ This configuration option stores CSE RW FW version in CBMEM area.
+ This information can be used to identify if the CSE firmware update is successful
+ by comparing the currently running CSE RW firmware version against CSE version
+ belongs to the CONFIG_SOC_INTEL_CSE_RW_VERSION (decided statically while
+ building the AP FW image).
+
+ The way to retrieve the CSE firmware version is by sending the HECI command to
+ read the CSE Boot Partition (BP) info. The cost of sending HECI command to read
+ the CSE FW version is between 7ms-20ms (depending on the SoC architecture) hence,
+ ensure this feature is platform specific and only enabled for the platform
+ that would like to store the CSE version into the CBMEM.
+
config SOC_INTEL_STORE_ISH_FW_VERSION
bool
default n
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index ea956a7..14637ce 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1438,7 +1438,7 @@
*/
static void cse_final(struct device *dev)
{
- if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
+ if (CONFIG(SOC_INTEL_STORE_CSE_FW_VERSION))
intel_cse_get_rw_version();
/*
* SoC user can have two options for sending EOP:
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index dd3f173..d3fcec7 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -1304,7 +1304,8 @@
cse_fw_sync();
/* Store the CSE RW Firmware Version into CBMEM */
- cse_store_rw_fw_version();
+ if (CONFIG(SOC_INTEL_STORE_CSE_FW_VERSION))
+ cse_store_rw_fw_version();
/*
* Store the ISH RW Firmware Version into CBMEM if ISH partition
* is available
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Hello Harsha B R, Jamie Ryu, Jay Patel, Kapil Porwal, Subrata Banik, Tarun Tuli, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Verified+1 by build bot (Jenkins)
Change subject: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG
......................................................................
mb/google/rex: Configure ISH GPIO's based on FW_CONFIG
Configures ISH related GPIO's based on FW_CONFIG obtained from CBI.
BUG=b:280329972,b:283023296
TEST= Set bit 21 of FW_CONFIG with CBI
Boot rex board
Check that ISH is enabled, loaded, and functional
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749
---
M src/mainboard/google/rex/variants/rex0/fw_config.c
1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/75525/10
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Henry Sun has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75872?usp=email )
Change subject: mb/google/nissa/var/gothrax: Add GPIO table for gothrax
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
Patchset:
PS6:
Adding Derek for review and approval. Thanks!
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75959?usp=email )
Change subject: soc/intel/cannonlake/chip.h: Use boolean type where applicable
......................................................................
Patch Set 3: Code-Review+2
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Hello Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/76042?usp=email
to look at the new patch set (#2).
Change subject: util/qemu: Add config for AArch64
......................................................................
util/qemu: Add config for AArch64
Most arguments taken from the Kconfig help. RAM needs to be >= 531M,
as coreboot is linked to reside between 512M..531M.
Change-Id: Id7f23918a786bc126188d5caf285e9f532dbb0ed
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M util/qemu/Makefile.inc
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/76042/2
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