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The following approvals got outdated and were removed:
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Change subject: soc/intel/meteorlake: Add support for crashlog
......................................................................
soc/intel/meteorlake: Add support for crashlog
Capture crashlog records from CPU PUNIT SRAM, SOC PMC SRAM and,
IOE SRAM. Crashlog records for IOE SRAM is discovered by
parsing SOC PMC SRAM records.
BUG=b:262501347
TEST=Able to trigger Crashlog, BERT table gets generated and decodes
as expected.
Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
---
M src/soc/intel/meteorlake/Makefile.inc
A src/soc/intel/meteorlake/crashlog.c
A src/soc/intel/meteorlake/include/soc/crashlog.h
M src/soc/intel/meteorlake/include/soc/pci_devs.h
4 files changed, 524 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/74769/25
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Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel.
Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel,
I'd like you to reexamine a change. Please visit
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Change subject: include/intelblocks/post_code.h: Change post code prefix to POSTCODE
......................................................................
include/intelblocks/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
filedir=src/soc/intel/common/block/include/intelblocks/post_codes.h
sed -i'' '1,${s/#define POST_/#define POSTCODE_/g;}' $filedir
myArray=`grep -e "^#define POSTCODE_" $filedir | grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`
for str in ${myArray[@]}; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r POST_$splitstr src | cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"
done
Change-Id: Ie84abb6cfd467dd51c0d62111306969ecab5313b
Signed-off-by: lilacious <yuchenhe126(a)gmail.com>
---
M src/drivers/amd/agesa/cache_as_ram.S
M src/soc/amd/common/block/cpu/car/cache_as_ram.S
M src/soc/amd/common/block/cpu/noncar/pre_c.S
M src/soc/amd/common/block/include/amdblocks/post_codes.h
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/post_codes.h
7 files changed, 25 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/76045/2
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Yuchen He has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76047?usp=email )
Change subject: commonlib/post_codes.h: Change POST_EXIT_PCI_SCAN_BUS description
......................................................................
commonlib/post_codes.h: Change POST_EXIT_PCI_SCAN_BUS description
Description of POST_EXIT_PCI_SCAN_BUS indicates the opposite of what
its name suggests. Secondly, POST_ENTER_PCI_SCAN_BUS and
POST_EXIT_PCI_SCAN_BUS have identical comments, which appears to be
an error.
Change the description accordingly.
Change-Id: Ifc920651255bacf033cac39f0208d817f9ee84fc
Signed-off-by: lilacious <yuchenhe126(a)gmail.com>
---
M src/commonlib/include/commonlib/console/post_codes.h
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/76047/1
diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h
index a8a8d95..732e658 100644
--- a/src/commonlib/include/commonlib/console/post_codes.h
+++ b/src/commonlib/include/commonlib/console/post_codes.h
@@ -85,9 +85,9 @@
#define POST_ENTER_PCI_SCAN_BUS 0x24
/**
- * \brief Entry into pci_scan_bus
+ * \brief Exit out of pci_scan_bus
*
- * Entered pci_scan_bus()
+ * Exited pci_scan_bus()
*/
#define POST_EXIT_PCI_SCAN_BUS 0x25
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Attention is currently required from: Martin L Roth, Patrick Georgi, Paul Menzel.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75879?usp=email )
Change subject: Docs/contrib/coding_style: Document the preference for if() vs #if
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
File Documentation/contributing/coding_style.md:
https://review.coreboot.org/c/coreboot/+/75879/comment/88b3c88a_fbd99ac1 :
PS1, Line 539: ifdef
Should we go further and say that #ifdef is just forbidden entirely? With the way CONFIG() works in coreboot it should basically always be an error. The only thing where it still seems to be used is `#ifdef __SIMPLE_DEVICE__` and it would probably be better if we refactored that to work more like the other stuff in rules.h (e.g. `#if ENV_SIMPLE_DEVICE`).
Mixing #if and #ifdef can easily lead to mistakes when you accidentally use #ifdef on something that's defined to 0 when it is off, so I think it would be nice to outlaw (and linter-enforce) #ifdef entirely and use the more visually obvious `#if defined()` in places where we actually intentionally want to check for the definition of a macro (e.g. in rules.h itself).
https://review.coreboot.org/c/coreboot/+/75879/comment/e21cdf97_5438ef9f :
PS1, Line 547: shouldn't
nit: maybe say "should usually not be a need" because there are some rare cases where there really is a need (e.g. https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… where it includes separate headers defining the same function depending on Kconfig... not saying that was necessarily the best design to begin with, but that's what we have there at the moment).
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Attention is currently required from: Andrey Petrov, Angel Pons, Arthur Heymans, Boris Mittelberg, Caveh Jalali, Christian Walter, Felix Held, Felix Singer, Fred Reitberger, Jakub Czapiga, Jason Glenesk, Johnny Lin, Julius Werner, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Raul Rangel, Subrata Banik, Tarun Tuli, Tim Chu, Werner Zeh, Yu-Ping Wu.
Hello Andrey Petrov, Angel Pons, Arthur Heymans, Boris Mittelberg, Caveh Jalali, Christian Walter, Felix Held, Felix Singer, Fred Reitberger, Jakub Czapiga, Jason Glenesk, Johnny Lin, Julius Werner, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Raul Rangel, Subrata Banik, Tarun Tuli, Tim Chu, Werner Zeh, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/76043?usp=email
to look at the new patch set (#4).
Change subject: commonlib/console/post_code.h: Change post code prefix to POSTCODE
......................................................................
commonlib/console/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \
src/commonlib/include/commonlib/console/post_codes.h;
myArray=`grep -e "^#define POSTCODE_" \
src/commonlib/include/commonlib/console/post_codes.h | \
grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`;
for str in ${myArray[@]}; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r POST_$splitstr src | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
grep -r "POST_$splitstr" util/cbfstool | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
done
Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Signed-off-by: lilacious <yuchenhe126(a)gmail.com>
---
M src/arch/x86/acpi_s3.c
M src/arch/x86/c_start.S
M src/arch/x86/postcar_loader.c
M src/arch/x86/tables.c
M src/commonlib/include/commonlib/console/post_codes.h
M src/cpu/intel/car/core2/cache_as_ram.S
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/p3/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/qemu-x86/cache_as_ram_bootblock.S
M src/cpu/x86/entry16.S
M src/cpu/x86/entry32.S
M src/device/device.c
M src/device/pci_device.c
M src/drivers/amd/agesa/cache_as_ram.S
M src/drivers/intel/fsp1_1/cache_as_ram.S
M src/drivers/intel/fsp1_1/car.c
M src/drivers/intel/fsp1_1/fsp_util.c
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/notify.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/drivers/pc80/rtc/post.c
M src/ec/google/wilco/commands.c
M src/lib/hardwaremain.c
M src/lib/prog_loaders.c
M src/lib/ramtest.c
M src/northbridge/intel/haswell/broadwell_mrc/raminit.c
M src/northbridge/intel/haswell/haswell_mrc/raminit.c
M src/northbridge/intel/i440bx/raminit.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/security/tpm/tspi/tspi.c
M src/security/vboot/vboot_logic.c
M src/soc/amd/cezanne/cpu.c
M src/soc/amd/common/block/cpu/car/cache_as_ram.S
M src/soc/amd/common/block/cpu/noncar/pre_c.S
M src/soc/amd/common/block/cpu/smm/finalize.c
M src/soc/amd/glinda/cpu.c
M src/soc/amd/mendocino/cpu.c
M src/soc/amd/phoenix/cpu.c
M src/soc/amd/picasso/cpu.c
M src/soc/amd/stoneyridge/cpu.c
M src/soc/intel/alderlake/finalize.c
M src/soc/intel/baytrail/romstage/raminit.c
M src/soc/intel/broadwell/finalize.c
M src/soc/intel/broadwell/raminit.c
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/finalize.c
M src/soc/intel/common/acpi/platform.asl
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/p2sb/p2sblib.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/elkhartlake/finalize.c
M src/soc/intel/jasperlake/finalize.c
M src/soc/intel/meteorlake/chip.c
M src/soc/intel/meteorlake/finalize.c
M src/soc/intel/skylake/finalize.c
M src/soc/intel/tigerlake/finalize.c
M src/soc/intel/xeon_sp/finalize.c
M src/southbridge/intel/common/finalize.c
M src/southbridge/intel/i82801gx/lpc.c
M src/vendorcode/google/chromeos/cr50_enable_update.c
M util/cbfstool/eventlog.c
68 files changed, 234 insertions(+), 234 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/76043/4
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Yuchen He has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76043?usp=email )
Change subject: commonlib/console/post_code.h: Change post code prefix to POSTCODE
......................................................................
Patch Set 3:
(1 comment)
File src/lib/hardwaremain.c:
https://review.coreboot.org/c/coreboot/+/76043/comment/340199fd_a742619b :
PS2, Line 63: .post_code = POST_ ## state_, \
Issue
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Attention is currently required from: Andrey Petrov, Angel Pons, Arthur Heymans, Boris Mittelberg, Caveh Jalali, Christian Walter, Felix Held, Felix Singer, Fred Reitberger, Jakub Czapiga, Jason Glenesk, Johnny Lin, Julius Werner, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Raul Rangel, Subrata Banik, Tarun Tuli, Tim Chu, Werner Zeh, Yu-Ping Wu, Yuchen He.
Hello Andrey Petrov, Angel Pons, Arthur Heymans, Boris Mittelberg, Caveh Jalali, Christian Walter, Felix Held, Felix Singer, Fred Reitberger, Jakub Czapiga, Jason Glenesk, Johnny Lin, Julius Werner, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Raul Rangel, Subrata Banik, Tarun Tuli, Tim Chu, Werner Zeh, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/76043?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: commonlib/console/post_code.h: Change post code prefix to POSTCODE
......................................................................
commonlib/console/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' src/commonlib/include/commonlib/console/post_codes.h
myArray=`grep -e "^#define POSTCODE_" src/commonlib/include/commonlib/console/post_codes.h | grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`
for str in ${myArray[@]}; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r POST_$splitstr src | cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"
done
Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Signed-off-by: lilacious <yuchenhe126(a)gmail.com>
---
M src/arch/x86/acpi_s3.c
M src/arch/x86/c_start.S
M src/arch/x86/postcar_loader.c
M src/arch/x86/tables.c
M src/commonlib/include/commonlib/console/post_codes.h
M src/cpu/intel/car/core2/cache_as_ram.S
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/p3/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/qemu-x86/cache_as_ram_bootblock.S
M src/cpu/x86/entry16.S
M src/cpu/x86/entry32.S
M src/device/device.c
M src/device/pci_device.c
M src/drivers/amd/agesa/cache_as_ram.S
M src/drivers/intel/fsp1_1/cache_as_ram.S
M src/drivers/intel/fsp1_1/car.c
M src/drivers/intel/fsp1_1/fsp_util.c
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/notify.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/drivers/pc80/rtc/post.c
M src/ec/google/wilco/commands.c
M src/lib/hardwaremain.c
M src/lib/prog_loaders.c
M src/lib/ramtest.c
M src/northbridge/intel/haswell/broadwell_mrc/raminit.c
M src/northbridge/intel/haswell/haswell_mrc/raminit.c
M src/northbridge/intel/i440bx/raminit.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/security/tpm/tspi/tspi.c
M src/security/vboot/vboot_logic.c
M src/soc/amd/cezanne/cpu.c
M src/soc/amd/common/block/cpu/car/cache_as_ram.S
M src/soc/amd/common/block/cpu/noncar/pre_c.S
M src/soc/amd/common/block/cpu/smm/finalize.c
M src/soc/amd/glinda/cpu.c
M src/soc/amd/mendocino/cpu.c
M src/soc/amd/phoenix/cpu.c
M src/soc/amd/picasso/cpu.c
M src/soc/amd/stoneyridge/cpu.c
M src/soc/intel/alderlake/finalize.c
M src/soc/intel/baytrail/romstage/raminit.c
M src/soc/intel/broadwell/finalize.c
M src/soc/intel/broadwell/raminit.c
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/finalize.c
M src/soc/intel/common/acpi/platform.asl
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/p2sb/p2sblib.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/elkhartlake/finalize.c
M src/soc/intel/jasperlake/finalize.c
M src/soc/intel/meteorlake/chip.c
M src/soc/intel/meteorlake/finalize.c
M src/soc/intel/skylake/finalize.c
M src/soc/intel/tigerlake/finalize.c
M src/soc/intel/xeon_sp/finalize.c
M src/southbridge/intel/common/finalize.c
M src/southbridge/intel/i82801gx/lpc.c
M src/vendorcode/google/chromeos/cr50_enable_update.c
67 files changed, 181 insertions(+), 181 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/76043/3
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Gerrit-Change-Number: 76043
Gerrit-PatchSet: 3
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