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Hello Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun Tuli,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/intel/meteorlake: Rename shared sram aliases
......................................................................
soc/intel/meteorlake: Rename shared sram aliases
Rename share sram aliases for IOE and PMC to make them
more readable.
pci device 13.3 is IOE shared sram
pci device 14.2 is PMC shared sram
Rename them in SOC code as well as mainboard to make sure
the patch builds for the relevant boards.
BUG=b:262501347
TEST=Able to build.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
Change-Id: I02a8cacc075f396549703d7a008382e76258f865
---
M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
M src/soc/intel/meteorlake/chipset.cb
4 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/75999/2
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76043?usp=email )
Change subject: commonlib/console/post_code.h: Change post code prefix to POSTCODE
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Change subject: mb/google/brya/acpi: Set polling timing for DL23 and LD23 to 2ms
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/google/brya/acpi: Set power down delay to 2ms after PEXVDD
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Change subject: soc/intel/meteorlake: Add support for crashlog
......................................................................
Patch Set 25:
(2 comments)
Patchset:
PS23:
> > > 1. I don’t see any redundant entries. […]
I will send the log.
>my question is how to understand from the above entry which one is for SOC.PMC and IOE.PMC?
Tag = 0 for SOC PMC
Tag = 1 for IOE
File src/soc/intel/meteorlake/crashlog.c:
https://review.coreboot.org/c/coreboot/+/74769/comment/1cc34e82_dea78b36 :
PS24, Line 63: pcireg = pci_read_config16(sram_dev, PCI_COMMAND);
: pcireg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
: pci_write_config16(sram_dev, PCI_COMMAND, pcireg);
> can we use `pci_update_config16`?
Done
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Change subject: mainboard/google/rex: Enable crashlog
......................................................................
Patch Set 18:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74770/comment/3527c433_eb080223 :
PS18, Line 10: shared_sram
> please mention which SRAM is for IOE and PMC
Done
https://review.coreboot.org/c/coreboot/+/74770/comment/6914a816_fc3fba88 :
PS18, Line 13: Bug
> BUG
Done
File src/mainboard/google/rex/variants/rex0/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/74770/comment/ffc17e1f_b86ad373 :
PS18, Line 838: device shared_sram2 on end
> device ref shared_sram2 on end <--- move this line at 352
Done
https://review.coreboot.org/c/coreboot/+/74770/comment/87dc8c90_d613e789 :
PS18, Line 839: device shared_sram on end
> device ref shared_sram on end <--- move this line at 415
Done
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Change subject: soc/intel/meteorlake: Rename shared sram aliases
......................................................................
soc/intel/meteorlake: Rename shared sram aliases
Rename share sram aliases for IOE and PMC to make them
more readable.
pci device 13.3 is IOE shared sram
pci device 14.2 is PMC shared sram
Rename them in SOC code as well as mainboard to make sure
the patch builds for the relevant boards.
BUG=b:262501347
TEST=Able to build.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
Change-Id: I02a8cacc075f396549703d7a008382e76258f865
---
M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
M src/soc/intel/meteorlake/chipset.cb
3 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/75999/1
diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
index 9a71e95..bfe991b 100644
--- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
@@ -57,7 +57,7 @@
device ref igpu on end
device ref dtt on end
device ref xhci on end
- device ref shared_sram on end
+ device ref pmc_shared_sram on end
device ref heci1 on end
device ref uart0 on end
device ref soc_espi on
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
index bd5b0bb..5297ce2 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
@@ -71,7 +71,7 @@
device ref igpu on end
device ref dtt on end
device ref xhci on end
- device ref shared_sram on end
+ device ref pmc_shared_sram on end
device ref heci1 on end
device ref uart0 on end
device ref soc_espi on
diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb
index 6a9c26a..b98e4f3 100644
--- a/src/soc/intel/meteorlake/chipset.cb
+++ b/src/soc/intel/meteorlake/chipset.cb
@@ -83,7 +83,7 @@
device pci 13.0 alias ioe_p2sb hidden end
device pci 13.1 alias ieh2 off end
device pci 13.2 alias pmc2 hidden end
- device pci 13.3 alias shared_sram2 off end
+ device pci 13.3 alias ioe_shared_sram off end
device pci 14.0 alias xhci off
chip drivers/usb/acpi
register "type" = "UPC_TYPE_HUB"
@@ -128,7 +128,7 @@
end
end
device pci 14.1 alias usb_otg off end
- device pci 14.2 alias shared_sram off end
+ device pci 14.2 alias pmc_shared_sram off end
device pci 14.3 alias cnvi_wifi off end
device pci 14.5 alias ieh off end
device pci 15.0 alias i2c0 off end
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Hello Eric Lai, Kapil Porwal, Subrata Banik, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Code-Review+2 by Eric Lai
Change subject: mainboard/google/rex: Enable crashlog
......................................................................
mainboard/google/rex: Enable crashlog
Enable crashlog for rex. Select config options SOC_INTEL_CRASHLOG,
and SOC_INTEL_IOE_DIE_SUPPORT. Also enable ioe_shared_sram and
pmc_shared_sram devices.
BUG=b:262501347
TEST=Able to trigger Crashlog, BERT table gets generated and decodes
as expected.
Change-Id: I3d3a9fb41d1293f021ad9de9b29c756cb7559373
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
---
M src/mainboard/google/rex/Kconfig
M src/mainboard/google/rex/variants/rex0/overridetree.cb
2 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/74770/19
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Code-Review+2 by Eric Lai, Code-Review+2 by Kapil Porwal, Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins)
The change is no longer submittable: Code-Review and Verified are unsatisfied now.
Change subject: soc/intel/common: Print crashlog size info in hex
......................................................................
soc/intel/common: Print crashlog size info in hex
Print crashlog size information in hex to be consistent with
other prints.
BUG=b:262501347
TEST=Values printed in hex.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
Change-Id: Ieb5498e702497bfbc2b4d5396d5b760a0010f5de
---
M src/soc/intel/common/block/acpi/acpi_bert.c
1 file changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/75910/5
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ieb5498e702497bfbc2b4d5396d5b760a0010f5de
Gerrit-Change-Number: 75910
Gerrit-PatchSet: 5
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